Asynchronous System-on-Chip Interconnect (Distinguished Dissertations)

John Bainbridge

ISBN 10: 185233598X / ISBN 13: 9781852335984

Editore: Springer, 2002

Riguardo questo articolo

Gebraucht - Wie neu Loc 942.

Codice articolo 795

Dati bibliografici

• Titolo: Asynchronous System-on-Chip Interconnect (Distinguished Dissertations)
• Editore: Springer
• Data di pubblicazione: 2002
• Lingua: Inglese
• ISBN 10: 185233598X
• ISBN 13: 9781852335984
• Rilegatura: Gebundene Ausgabe
• Condizione: Wie neu
• Peso: 364 grammi

Descrizione articolo

Riassunto

Asynchronous System-on-Chip Interconnect describes the use of an entirely asynchronous system-bus for the modular construction of integrated circuits. Industry is just awakening to the benefits of asynchronous design in avoiding the problems of clock-skew and multiple clock-domains, an din parallel with this is coming to grips with Intellectual Property (IP) based design flows which emphasise the need for a flexible interconnect strategy. In this book, John Bainbridge investigates the design of an asynchronous on-chip interconnect, looking at all the stages of the design from the choice of wiring layout, through asynchronous signalling protocols to the higher level problems involved in supporting split transactions. The MARBLE bus (the first asynchronous SoC bus) used in a commercial demonstrator chip containing a mixture of asynchronous and synchronous macrocells is used as a concrete example throughout the book.

Contenuti

INTRODUCTIONAsynchronous design and its advantagesDisadvantages of asynchronous designBook overviewPublicationsASYNCHRONOUS DESIGNIntroductionAsynchronous designSummarySYSTEM LEVEL INTERCONNECT PRINCIPLESPoint-to-point communication pathsMultipoint interconnect topologyBus protocol issuesInterconnect performance objectivesCommercial on-chip busesSummaryTHE PHYSICAL (WIRE) LAYERWire theoryElectrical and physical characteristicsTerminationCrosstalkSummaryTHE LINK LAYERCentralised vs distributed interfacesSignalling conventionData encodingHandshake sourcesBidirectional data transferMultiple initiators on one channelMultiple targetsMultipoint bus-channel interfacesMARBLE's link layer channelsSummaryPROTOCOL LAYERTransfer phasesExceptionsDefer and bridgingMapping transfer phases onto channel cyclesTransfer cycle routingTransfer cycle initiationMARBLE's dual channel bus architectureTRANSACTION LAYERSplit transactionsResponse orderingMARBLE's transaction layerMARBLE: A DUAL CHANNEL SPLIT TRANSFER BUSMARBLE protocol and signal summaryBus transaction interface implementationMARBLE in the AMULET3H systemSummaryEVALUATIONThe MARBLE testbedSimulation of MARBLE in AMULET3HAnalysis of delay distributionHardware requirementsComparison with synchronous alternativesCONCLUSIONAdvantages and disadvantages of MARBLEImproving the MARBLE busAlternative interconnect solutions and future workThe future of asynchronous SoC interconnect?APPENDIX A: MARBLE SCHEMATICSREFERENCESINDEX