Automated Calibration of Modulated Frequency Synth. Questo articolo non è disponibile.Automated Calibration of Modulated Frequency Synth

List of Figures. List of Tables. Foreword by Charles G. Sodini. Acknowledgments. 1: Introduction. 1.1 Outline. 1.2. Choice of Modulation Affects Battery Life. 1.3. Classes of Modulation. 1.3.1. Linear Modulation. 1.3.2. Constant Envelope Modulation. 1.4. GFSK and GMSK. 1.5. Coherent Versus Noncoherent Demodulation. 1.5.1. Modulator Requirements for Coherent Detection. 1.6. Chapter 1 Summary. 2: Architectures. 2.1. Direct VCO Modulation. 2.2. Quadrature Modulator. 2.3. Open Loop Modulation with PLL Tuning. 2.4. Modulated Fractional-N Synthesizer. 2.5. Calibrated Synthesizer Architecture. 2.6. Chapter 2 Summary. 3: System Requirements. 3.1. Total Phase Error Variance. 3.2 Chapter 3 Summary. 4: Automatic Calibration System. 4.1. PLL Mismatch Model. 4.2. The Gain Error Detector. 4.3. Track and Hold Modification to the Error Detector. 4.4. Simulated Gain Error Detector Performance. 4.5. Carrier Phase Tracking. 4.5.1. Sources of Carrier Phase Error. 4.5.2. Effect of Phase Offset and Drift on the Gain Error Detector. 4.5.3. Digital Phase Locked Loop Addition. 4.6. Complete Gain Error Detector. 4.7. Acquisition Range and Digital Coarse Calibration. 4.8. Application to Other Architectures. 4.9. Chapter 4 Summary. 5: Implementation Details. 5.1. Discrete Prototype. 5.1.1. Charge Pump and Loop Filter. 5.1.2. VCO. 5.1.3. RF Output Filter and Buffer. 5.1.4. RF Phase Quantizer. 5.1.5. Quadrature Sampler Approach. 5.1.6. Board Level Phase Quantizer Circuit Details. 5.1.7. Digital Calibration DAC. 5.1.8. Multimodulus Divider. 5.1.9. Reference Oscillator. 5.1.10. Digital Signal Processing. 5.2. Integrated Circuit Process Technology. 5.2.1. Varactor. 5.2.2. Bondwire Inductors. 5.3. RF Phase Quantizer. 5.3.1. RF Phase Quantizer Circuit Details. 5.3.2. Phase Quantizer Comments. 5.3.3. RF Interconnect. 5.4. Digital Building Blocks. 5.4.1. Flip-Flops. 5.4.2. Adders. 5.5. Reference Error Filter. 5.5.1. Decimator Design. 5.5.2. Discrete Time Filter Approximation. 5.5.3. Digital Filter Architectures. 5.5.4. SPT Approximation. 5.6. Digital Phase Locked Loop and Phase Error Measurement. 5.6.1. DPLL Loop Dynamics. 5.6.2. Carrier Phase Detector with Track and Hold. 5.6.3. Upsampler. 5.7. Gain Control Multiplier and Error Amp. 5.8. 1.8 GHz VCO. 5.9. Main Synthesizer. 5.10. &Dgr;-&Sgr; Modulator. 5.11. Chapter 5 Summary. 6: Experimental Results. 6.1. Discrete Prototype Results. 6.1.1. Discrete Prototype GFSK/GMSK Eye Pattern and Spectrum. 6.1.2. Discrete Prototype RF Phase Quantizer. 6.2. Integrated Circuit Test Environment. 6.3. Automatic Calibration Results. 6.3.1. GFSK/GMSK Eye Pattern and Spectrum. 6.3.2. 4 Level GFSK Eye Pattern and Spectrum. 6.3.3. Calib