Compilation Techniques for Reconfigurable Architectures

Pedro C. Diniz

ISBN 10: 0387096701 / ISBN 13: 9780387096704

Editore: Springer US, Springer New York, 2008

Riguardo questo articolo

Druck auf Anfrage Neuware - Printed after ordering - The extreme exibility of recon gurable architectures and their performance pot- tial have made them a vehicle of choice in a wide range of computing domains, from rapid circuit prototyping to high-performance computing. The increasing availab- ity of transistors on a die has allowed the emergence of recon gurable architectures with a large number of computing resources and interconnection topologies. To - ploit the potential of these recon gurable architectures, programmers are forced to map their applications, typically written in high-level imperative programming l- guages, such as C or MATLAB, to hardware-oriented languages such as VHDL or Verilog. In this process, they must assume the role of hardware designers and software programmers and navigate a maze of program transformations, mapping, and synthesis steps to produce ef cient recon gurable computing implementations. The richness and sophistication of any of these application mapping steps make the mapping of computations to these architectures an increasingly daunting process. It is thus widely believed that automatic compilation from high-level programming languages is the key to the success of recon gurable computing. This book describes a wide range of code transformations and mapping te- niques for programs described in high-level programming languages, most - tably imperative languages, to recon gurable architectures.

Codice articolo 9780387096704

Dati bibliografici

• Titolo: Compilation Techniques for Reconfigurable Architectures
• Editore: Springer US, Springer New York
• Data di pubblicazione: 2008
• Lingua: Inglese
• ISBN 10: 0387096701
• ISBN 13: 9780387096704
• Rilegatura: Buch
• Condizione: Neu
• Dimensioni: 209 L x 132 A x 18 P (millimetri) 209 millimetri di larghezza per 132 millimetri di altezza per 18 millimetri di profondità
• Peso: 351 grammi

Descrizione articolo

Riassunto

The extreme ?exibility of recon?gurable architectures and their performance pot- tial have made them a vehicle of choice in a wide range of computing domains, from rapid circuit prototyping to high-performance computing. The increasing availab- ity of transistors on a die has allowed the emergence of recon?gurable architectures with a large number of computing resources and interconnection topologies. To - ploit the potential of these recon?gurable architectures, programmers are forced to map their applications, typically written in high-level imperative programming l- guages, such as C or MATLAB, to hardware-oriented languages such as VHDL or Verilog. In this process, they must assume the role of hardware designers and software programmers and navigate a maze of program transformations, mapping, and synthesis steps to produce ef?cient recon?gurable computing implementations. The richness and sophistication of any of these application mapping steps make the mapping of computations to these architectures an increasingly daunting process. It is thus widely believed that automatic compilation from high-level programming languages is the key to the success of recon?gurable computing. This book describes a wide range of code transformations and mapping te- niques for programs described in high-level programming languages, most - tably imperative languages, to recon?gurable architectures.

Dalla quarta di copertina

This book describes a wide range of code transformations and mapping techniques for compiling programs written in high-level programming languages to reconfigurable architectures. While many of these transformations and mapping techniques have been developed in the context of compilation for traditional architectures and high-level synthesis, their application to reconfigurable architectures poses a whole new set of challenges- particularly when targeting fine-grained reconfigurable architectures such as contemporary Field-Programmable Gate-Arrays (FPGAs).

Organized in eight chapters, this book provides a helpful structure for practitioners and graduate students in the area of computer science and electrical and computer engineering to effectively map computations to reconfigurable architectures.

Key Features:

• Introduces the reader to hardware compilation and reconfigurable computing architectures.
• Presents a range of compiler code transformations and mapping techniques focusing on imperative programming languages.
• Allows the reader to bridge the gap between the software compilation and the hardware compilation and synthesis domains.
• Brings a number of compilation techniques together into one structured source, and includes representative examples of their applications.

• Provides a historical perspective on representative compilation research efforts over the last 15 years.