Riassunto
DEFECT PROPORTION OF DETECTION INITIAL RATE DETECTION RATE INSPECTOR 3 COMPLEXITY OF TIMES PAN OF PERFORMING o~ ________________________ o~ ______________________ __ -;. INSPECTION TASK -;. VISUAL INSPECTION Fagure 1. Trends in relations between the complexity of inspection tasks, defect detection rates (absolute and relative), and inspection time. Irrespective of the necessities described above, and with the excep tion of specific generic application systems (e.g., bare-board PCB inspection, wafer inspection, solder joint inspection, linewidth measure ment), vision systems are still not found frequently in today's electronics factories. Besides cost, some major reasons for this absence are: 1. The detection robustness or accuracy is still insufficient. 2. The total inspection time is often too high, although this can frequently be attributed to mechanical handling or sensing. 3. There are persistent gaps among process engineers, CAD en gineers, manufacturing engineers, test specialists, and computer vision specialists, as problems dominate the day-to-day interac tions and prevent the establishment of trust. 4. Computer vision specialists sometimes still believe that their contributions are universal, so that adaptation to each real problem becomes tedious, or stumbles over the insufficient availabIlity of multidisciplinary expertise. Whether we like it or not, we must still use appropriate sensors, lighting, and combina tions of algorithms for each class of applications; likewise, we cannot design mechanical handling, illumination, and sensing in isolation from each other.
Contenuti
and Organization of the Book.- I. Applications and Systems Aspects.- 1. Vision System Components.- 1.1. Video Sensors.- 1.1.1. Video Cameras.- 1.1.2. Charge Transfer Devices (CTD).- 1.1.3. Shape of the Sensor.- 1.1.4. Sensor Resolution.- 1.1.5. Sensitivity.- 1.1.6. Dynamic Range.- 1.1.7. Signal-to-Noise Ratio (SNR).- 1.1.8. Geometric Distortion.- 1.1.9. Readout Speed.- 1.1.10. Spectral Sensitivity.- 1.1.11. Lag.- 1.1.12. Camera Synchronization.- 1.1.13. Nonuniformities.- 1.2. CCIR 625 Video Standard.- 1.3. Scanning of the Digitized Image.- 1.4. Strobe Lighting.- 1.4.1. Introduction.- 1.4.2. Motion Freeze.- 1.4.3. Flash Selection.- 1.4.4. Strobe Synchronization.- 1.4.5. Strobe Beam Geometry Configuration.- 1.4.6. Reflection Elimination.- 1.5. Image Content and Imperfections.- 1.5.1. Imperfections.- 1.5.2. Lighting Environments.- 1.5.3. Lighting Design.- 1.5.4. Image Compensation for Spatial Emissivity.- 1.6. Design Choices for the Vision System Specifications.- 1.6.1. Performance Requirements (R).- 1.6.2. Architecture (A).- 1.6.3. Vision System Design and Test Aids.- 1.7. Calculation of the Inspection Yield.- 1.7.1. Defect Detection Probability.- 1.7.2. Defect Probability from Area and Image Density.- 1.8. Total Inspection Costs.- 2. Imaging Microscopes for Microelectronics.- 2.1. Optical Microscope Attributes for Microelectronics.- 2.1.1. Microscope Lighting.- 2.1.2. Confocal Imaging.- 2.2. Electron Beam Inspection of ICs.- 2.2.1. Principle of Scanning Electron Microscopy (SEM).- 2.2.2. Voltage Resolution.- 2.2.3. Stroboscopy.- 2.2.4. Dynamic Fault Imaging (DFI) for Timing Problem Analysis.- 2.2.5. Thermal Gradient Imaging of Junctions.- 2.2.6. Scanning Transmission Electron Microscopy (STEM) for Cross-Sectional Analysis.- 2.3. Laser Scan Microscopy.- 2.3.1. Principle of Laser Scan Microscopy (LSM).- 2.3.2. Laser Spot Size.- 2.3.3. Laser Scanning Tomography (LST).- 2.3.4. Applications.- 2.4. Pulsed IR Microscopy.- 2.4.1. Dynamic Latch-Up Imaging.- 2.4.2. Static Substrate and Circuit Analysis.- 2.5. Imaging of Photoinduced Currents.- 2.5.1. Optical Beam-Induced Current (OBIC) Measurements.- 2.5.2. Laser-Based OBIC Photocurrent Calculation.- 2.5.3. Electron Beam-Induced (EBIC) Photocurrent Calculation.- 2.5.4. OBIC and EBIC Image Processing.- 3. Metrology in Electronic Devices and Substrates.- 3.1. Linewidth Measurement.- 3.2. Area Measurement.- 3.3. Surface Flatness and Profiling.- 3.3.1. Flatness Measures.- 3.3.2. Flatness Measurement.- 3.3.3. Flatness Display Images.- 3.3.4. Areas of Application.- 4. Inspection of Integrated Circuits and Gate Arrays.- 4.1. Inspection Standards.- 4.2. Inspection Procedure Implementation.- 4.3. Optical Setups for MIL-STD-883 Inspection Screens.- 4.4. Test Patterns.- 4.5. Optical Defect Features.- 4.6. Other Silicon IC Inspection Principles.- 4.7. Other III–V Compound IC Inspection Principles.- 4.8. Results of IC Inspection and Link to Other Test or Defect Analysis Methods.- 4.9. Surface and Depth Analysis of Semiconductors.- 4.9.1. Wavelength Dispersive X-Ray Spectrometry (WDX).- 4.9.2. Energy Dispersive X-Ray Spectrometry (EDX).- 4.9.3. Optical Beam-Induced Currents (OBIC).- 4.9.4. Photovoltage Spectroscopy (PVS).- 4.9.5. Deep-Level Transient Spectroscopy (DLTS).- 4.9.6. Secondary Ion Mass Spectrometry (SIMS).- 4.9.7. “Time-of-Flight” Mass Spectrometry.- 4.9.8. Scanning Auger Electron Spectrometry (SAM).- 4.10. Bubble Memory Inspection.- 4.11. Laser Trimming and Link Cutting.- 4.12. Inspection Implementation Aspects.- 4.13. Links between Inspection and Functional Testing.- 5. Sensor Fusion for Integrated Circuit Testing.- 5.1. Integrated Testing of ICs: Principles.- 5.2. Implementation of Integrated Precap Testing of Silicon ICs in Two IR Bands.- 5.3. Image Understanding of Defects in GaAs ICs by Sensor Fusion.- 5.3.1. Experimental Setup.- 5.3.2. Digital Image Processing.- 5.3.3. Knowledge-Based Interpretation.- 5.3.4. Experimental Results for III-V Compounds and Defect Correlation.- 6. Wafer Inspection.- 6.1. X-Y-Z Stage or Step-and-Repeat Accuracy.- 6.2. Wafer Flatness.- 6.3. Step Height Profile Mapping on Wafers.- 6.4. Nonetched Wafer Surface Inspection.- 6.5. Spatial Sampling in Nonetched Wafer Surface Inspection Systems.- 6.6. Wafer Probe Mark Inspection.- 6.7. Critical Dimensions and Macro Defect Inspection of Resist Patterns.- 7. Mask Repair and Inspection.- 7.1. Mask Repair.- 7.2. Mask Particle Detection or Reticle Error Check.- 7.3. Mask Metrology.- 7.4. Dual-Beam Mask Inspection.- 8. Knowledge-Based Processing.- 8.1. Principle of Knowledge-Based Processing.- 8.2. Architecture of a Knowledge-Based System.- 8.2.1. Knowledge Base (KB).- 8.2.2. Knowledge Representation (KR).- 8.2.3. Inference Procedure (IE).- 8.2.4. User and System Interfaces.- 8.3. Environmental Stress Knowledge Bases.- 9. Design Rule Verification.- 9.1. Introduction.- 9.2. Logic Architecture of Design Rule Verification Systems.- 9.3. Geometrical Attributes.- 9.4. Geometrical Validation Predicates.- 9.5. Electrical Validation Predicates.- 9.5.1. Circuit Extraction.- 9.5.2. Functional Testing.- 10. Printed Circuit Board (PCB) Inspection.- 10.1. Typical PCB Defects and Inspection Requirements.- 10.2. PCB Inspection Approaches.- 10.3. PCB Inspection System Architecture.- 10.4. PCB Illumination.- 10.5. PCB Annular Ring Inspection.- 10.6. PCB Conductor Width Measurement.- 10.7. Vision Feedback for PCB Drilling.- 10.8. Other PCB Inspection Sensors.- 10.9. Infrared PCB Inspection.- 10.10. Inspection of Multilayer Substrates.- 10.10.1. Introduction.- 10.10.2. Multilayer Inspection Approaches.- 10.11. Microfocus X-Ray Inspection of Multilayer PCBs.- 11. Inspection for Assembly Tasks.- 11.1. Mark Reading.- 11.2. 2-D Package Inspection (Lead, Label, Package Material).- 11.3. 3-D Package Inspection by Range/Intensity Images.- 11.4. Die Attach, Solder, and Bonding Inspection.- 11.5. Component Placement.- 11.5.1. Applications.- 11.5.2. SMD Placement.- 11.6. Missing or Improperly Mounted Components or Leads.- 11.6.1. Stuffed PCB Inspection.- 11.6.2. Other Applications.- 12. Knowledge-Based Printed Circuit Board Manufacturing.- 12.1. PCB Design.- 12.1.1. PCB Design Verification and Routing.- 12.1.2. PCB Layout.- 12.2. Bare-Board PCB Production.- 12.2.1. Tooling.- 12.2.2. PCB Inspection.- 12.2.3. Parts and Materials Transport.- 12.2.4. PCB/PWB Assembly Operations.- 12.3. Intelligent Wave Soldering.- 12.4. Stuffed PCB Inspection.- 12.5. Test and Rework.- 12.6. Integration.- 12.6.1. Configuration.- 12.6.2. Final Testing.- II. Vision Algorithms for Electronics Manufacturing.- 13. Image Quantization and Thresholding.- 13.1. Algorithm Quant-1: Quantization.- 13.2. Algorithm LUT-1: Lookup Table (LUT) Transforms.- 13.3. Algorithm Pseudo-1: Pseudo-Color Display.- 13.4. Algorithm Thresh-1: Fixed Threshold and Binarization.- 13.5. Algorithm Thresh-2: Threshold Selection by the Difference Histogram.- 14. Geometrical Corrections.- 14.1. Algorithm Geom-1: Geometrical Correction.- 14.2. Algorithm Geom-2: Interpolation.- 14.3. Algorithm Geom-3: Subpixel Edge Interpolation.- 14.4. Algorithm Calib-1: Sensor Calibration.- 15. Image Registration and Subtraction.- 15.1. Registration Problems.- 15.1.1. Registration Subproblems.- 15.1.2. Registration Procedures.- 15.1.3. Registration Errors.- 15.1.4. Registration versus Scan Type.- 15.1.5. Avoiding Registration.- 15.2. Algorithm Reg-1: Correlation.- 15.3. Algorithm Reg-2: Sequential Similarity Detection.- 15.4. Algorithm Templ-1: Physical Templates.- 15.5. Algorithm Circle-1: Circle Fitting.- 15.6. Algorithm Reg-3: Multiple Resolution Alignment.- 15.7. Algorithm Offset-1: Offset Calculation from Line Intersections for Fast Alignment.- 15.8. Algorithm Ruler-1: Validation of a Geometrical Model.- 15.9. Algorithm Subtr-1: Image Subtraction.- 16. Edge and Line Detection.- 16.1. Categorization of Algorithms.- 16.2. Algorithm Edge-1: Filtering-Based Edge Detection.- 16.3. Algorithm Edge-2: Edge Labeling for Line Detection.- 16.4. Algorithm Edge-3: Subpixel Edge Extraction.- 16.5. Algorithm Edge-4: Pyramidal Edge Detection.- 16.6. Algorithm Line-1: Edge Tracking.- 17. Region Segmentation and Boundaries.- 17.1. Introduction.- 17.2. Algorithm Segm-1: Region Growing.- 17.3. Algorithm Segm-2: Feature Domain Clustering.- 17.4. Algorithm Segm-3: Spatial Clustering.- 17.5. Algorithm Bound-1: Detection and Tracking of Boundaries.- 17.6. Algorithm Bound-2: Region Boundary Extraction.- 17.7. Algorithm AOI-1: Area of Interest (AOI) Processing.- 18. Geometry of Connected Components and Morphomathematics.- 18.1. Introduction.- 18.1.1. Goal.- 18.1.2. Adjacency (Connectedness) Relations.- 18.1.3. Labeled Image.- 18.1.4. Connected Components in Binary Images.- 18.2. Algorithm Label-1: Labeling of Connected Components in Binary Images.- 18.3. Algorithm Label-2: Relaxation Labeling.- 18.4. Algorithm Label-3: Position of a Connected Component.- 18.5. Algorithm Morph-1: Erosion and Dilation Operators.- 18.6. Algorithm Morph-2: Expansion-Contraction Flaw Detection.- 18.7. Algorithm Skeleton-1: Skeleton of a Connected Component.- 18.8. Algorithm Shrink-1: Shrinking of Connected Components or Lines.- 18.9. Algorithm Bridge-1: Matching Bridges in the Topological Cell Layouts.- 19. Feature Extraction.- 19.1. Introduction.- 19.2. Algorithm Feature-1: Attributes of a Connected Component.- 19.3. Algorithm Feature-2: Histogram Features of a Region.- 19.4. Algorithm Moments-1: Calculation of Moments of a Connected Component or Line.- 19.5. Algorithm Moments-2: Shape of a Line in Polar Coordinates.- 19.6. Algorithm Fuzzy-1: Figure of Merit for the IC Cell from a Fuzzy Language Description.- 19.7. Algorithm Feature-3: Binary Neighborhood Features.- 19.8. Algorithm Text-1: Texture Features.- 19.9. Algorithm Shade-1: Shade Features.- 20. Decision Logic.- 20.1. Algorithm Class-1: Pattern Classification.- 20.2. Algorithm Rule-1: Rule-Based Classification.- 21. Image Data Structures and Management.- 21.1. Algorithm Chain-1: Chain Code Representation of a Line.- 21.2. Algorithm Buff-1: Filtering Operations with Circular Buffering.- 21.3. Algorithm CAD-1: CAD Data Organization for Image Data Comparison.- 21.4. Algorithm Drill-1: Hole Drill Tape Organization.- 21.5. Algorithm Pat-1: File and Video Manipulations of Geometrical Reference Patterns.- 22. Conclusion: The Future of Computer Vision for Electronics Manufacturing.- Appendixes.- A. Glossary and Abbreviations.- B. Relevant Journals.- C. Units and Conversion Tables.- References.- Suggested Readings.
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