Constraining Designs for Synthesis and Timing Analysis

Sanjay Churiwala

ISBN 10: 1489989161 / ISBN 13: 9781489989161

Editore: Springer New York, Springer US Jun 2015, 2015

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This item is printed on demand - it takes 3-4 days longer - Neuware -This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints. 256 pp. Englisch. Codice articolo 9781489989161

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Titolo: Constraining Designs for Synthesis and ...

Casa editrice: Springer New York, Springer US Jun 2015

Data di pubblicazione: 2015

Legatura: Taschenbuch

Condizione: Neu

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Riassunto:

This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.

Informazioni sull?autore:

Sanjay Churiwala is an Electronics Engineer from IIT Kharagpur, with two decades of experience in EDA and VLSI. His interest areas include rule checking, synthesis, simulation, STA, Power and Clock Domain Crossings and Synchronization. He currently works at Hyderabad office of Xilinx.

Sridhar Gangadharan is a Senior Product Engineering Director for Timing Constraints Analysis and SpyGlass RTL Analysis Products at Atrenta. He has over 20 years of experience in the electronic design automation industry. His interest areas include RTL verification, timing closure, delay calculation and memory compilers. He holds a Bachelors degree in Computer Science and Engineering from Indian Institute of Technology in Delhi. He is based in San Jose, CA.