Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

José Pineda de Gyvez (u. a.)

ISBN 10: 1441942858 / ISBN 13: 9781441942852

Editore: Springer US, 2010

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Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits | José Pineda de Gyvez (u. a.) | Taschenbuch | xxi | Englisch | 2010 | Springer US | EAN 9781441942852 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.

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Dati bibliografici

• Titolo: Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
• Editore: Springer US
• Data di pubblicazione: 2010
• Lingua: Inglese
• ISBN 10: 1441942858
• ISBN 13: 9781441942852
• Rilegatura: Taschenbuch
• Condizione: Neu
• Dimensioni: 235 L x 155 A x 20 P (millimetri) 235 millimetri di larghezza per 155 millimetri di altezza per 20 millimetri di profondità
• Peso: 534 grammi
• Cataloghi dei venditori:
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Descrizione articolo

Riassunto

This book is essential to understand new test methodologies, algorithms and industrial practices. Without its insight into the physics of nano-metric technologies, it would be difficult to develop system-level test strategies that yield a high IC fault coverage. The work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. The 2nd edition of Defect Oriented Testing has been extensively updated with the addition of chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering to provide a link between defect sources and yield. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.

Dalla quarta di copertina

Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. In Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits state of the art of defect-oriented testing is presented from both a theoretical approach as well as from a practical point of view. Step-by-step handling of defect modeling, defect-oriented testing, yield modeling and its usage in common economics practices enables deeper understanding of concepts.

The progression developed in this book is essential to understand new test methodologies, algorithms and industrial practices. Without the insight into the physics of nano-metric technologies, it would be hard to develop system-level test strategies that yield a high IC fault coverage. Obviously, the work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.