Design & Analysis of Fast Adder using Quaternary Signed Digit (QSD)

Ravi Shankar Mishra

ISBN 10: 6139913497 / ISBN 13: 9786139913497

Editore: LAP LAMBERT Academic Publishing Okt 2018, 2018

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Neuware -Processors with high computational speed are necessary nowadays to solve problems faster and accurately. The speed of the processors depends on the speed of the basic processing unit. To increase the speed of these basic units we need fast adders and subtractors. This book discusses the QSD (Quaternary Sign Digit) adder unit which is faster than any other adders. The main problem of the adder is that the carry propagates from one stage to another increase. This can be reduced by using the QSD adder. It uses the base-four number system in which will help in reducing the number of bits required to store in the memory unit. This adder can be used for high-speed computing processors where the area is not a concern.Books on Demand GmbH, Überseering 33, 22297 Hamburg 52 pp. Englisch.

Codice articolo 9786139913497

Dati bibliografici

• Titolo: Design & Analysis of Fast Adder using Quaternary Signed Digit (QSD)
• Editore: LAP LAMBERT Academic Publishing Okt 2018
• Data di pubblicazione: 2018
• Lingua: Inglese
• ISBN 10: 6139913497
• ISBN 13: 9786139913497
• Rilegatura: Taschenbuch
• Condizione: Neu
• Dimensioni: 220 L x 150 A x 4 P (millimetri) 220 millimetri di larghezza per 150 millimetri di altezza per 4 millimetri di profondità
• Peso: 96 grammi

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Riassunto

Processors with high computational speed are necessary nowadays to solve problems faster and accurately. The speed of the processors depends on the speed of the basic processing unit. To increase the speed of these basic units we need fast adders and subtractors. This book discusses the QSD (Quaternary Sign Digit) adder unit which is faster than any other adders. The main problem of the adder is that the carry propagates from one stage to another increase. This can be reduced by using the QSD adder. It uses the base-four number system in which will help in reducing the number of bits required to store in the memory unit. This adder can be used for high-speed computing processors where the area is not a concern.