Design of Very High-Frequency Multirate Switched-Capacitor Circuits presents the theory and the corresponding CMOS implementation of the novel multirate sampled-data analog interpolation technique which has its great potential on very high-frequency analog frond-end filtering due to its inherent dual advantage of reducing the speed of data-converters and DSP core together with the specification relaxation of the post continuous-time filtering. This technique completely eliminates the traditional phenomenon of sampled-and-hold frequency-shaping at the lower input sampling rate. Also, in order to tackle physical IC imperfections at very high frequency, the state-of-the-art circuit design and layout techniques for high-speed Switched-Capacitor (SC) circuits are comprehensively discussed:
-Optimum circuit architecture tradeoff analysis
-Simple speed and power trade-off analysis of active elements
-High-order filtering response accuracy with respect to capacitor-ratio mismatches
-Time-interleaved effect with respect to gain and offset mismatch
-Time-interleaved effect with respect to timing-skew and random jitter with non-uniformly holding
-Stage noise analysis and allocation scheme
-Substrate and supply noise reduction
-Gain-and offset-compensation techniques
-High-bandwidth low-power amplifier design and layout
-Very low timing-skew multiphase generation
Two tailor-made optimum design examples in CMOS are presented. The first one achieves a 3-stage 8-fold SC interpolating filter with 5.5MHz bandwidth and 108MHz output sampling rate for a NTSC/PAL CCIR 601 digital video at 3 V. Another is a 15-tap 57MHz SC FIR bandpass interpolating filter with 4-fold sampling rate increase to 320MHz and the first-time embedded frequency band up-translation for DDFS system at 2.5V. The corresponding chip prototype achieves so far the highest operating frequency, highest filter order and highest center frequency with highest dynamic range under the lowest supply voltage when compared to the previously reported high-frequency SC filters in CMOS.
Dedication. Preface. Acknowledgment. List of Abbreviations. List of Figures. List of Tables. 1. Introduction. 1. High-Frequency Integrated Analog Filtering. 2. Multirate Switched-Capacitor Circuit Techniques. 3. Sampled-Data Interpolation Techniques. 4. Research Goals and Design Challenges. 2. Improved Multirate Polyphase-Based Interpolation Structures. 1. Introduction. 2. Conventional and Improved Analog Interpolation. 3. Polyphase Structures for Optimum-class Improved Analog Interpolation. 4. Multirate ADB Polyphase Structures. 5. Low-Sensitivity Multirate IIR Structures. 6. Summary. 3. Practical Multirate SC Circuit Design Considerations. 1.Introduction. 2. Power Consumption Analysis. 3. Capacitor-Ratio Sensitivity Analysis. 4. Finite Gain & Bandwidth Effects. 5. Input-Referred Offset Effects. 6. Phase Timing-Mismatch Effects. 7. Noise Analysis. 8. Summary. 4. Gain- and Offset-Compensation for Multirate SC Circuits. 1. Introduction. 2. Autozeroing and Correlated-Double Sampling Techniques. 3. AZ and CDS SC Delay Blocks with Mismatch-Free Property. 4. AZ and CDS SC Accumulators. 5. Design Examples. 6. Speed and Power Considerations. 7. Summary. 5. Design of a 108 MHz Multistage SC Video Interpolating Filter. 1. Introduction. 2. Optimum Architecture Design. 3. Circuit Design. 4. Circuit Layout. 5. Simulation Results. 6. Summary. 6. Design of a 320 MHz Frequency-Translated SC Bandpass Interpolating Filter. 1. Introduction. 2. Prototype System-Level Design. 3. Prototype Circuit-Level Design. 4. Layout Considerations. 5. Simulation Results. 6. Summary. 7. Experimental Results. 1. Introduction. 2. PCB Design. 3. Measurement Setup and Results. 4. Summary. 8. Conclusions. Appendix 1.Timing-Mismatch Errors with Nonuniformly Holding Effects. 1. Spectrum Expressions for IU-ON(SH) and IN-CON(SH). 2. Closed Form SINAD Expression for IU-ON(SH) and IN-CON(SH). 3. Closed Form SFDR Expression for IN-CON(SH) systems. 4. Spectrum Correlation of IN-OU(IS) and IU-ON(SH). Appendix 2. Noise Analysis For SC ADB Delay Line and Polyphase Subfilters. 1. Output Noise of ADB Delay Line. 2. Output Noise of Polyphase Subfilters. Appendix 3. Gain, Phase and Offset Errors for GOC MF SC Delay Circuit i and j. 1. GOC MF SC Delay Circuit i. 2. GOC MF SC Delay Circuit j.
