Design to Test

This book is the second edition of Design to Test. The first edition, written by myself and H. Frank Binnendyk and first published in 1982, has undergone several printings and become a standard in many companies, even in some countries. Both Frank and I are very proud of the success that our customers have had in utilizing the information, all of it still applicable to today's electronic designs. But six years is a long time in any technology field. I therefore felt it was time to write a new edition. This new edition, while retaining the basic testability prin­ ciples first documented six years ago, contains the latest material on state-of-the-art testability techniques for electronic devices, boards, and systems and has been completely rewritten and up­ dated. Chapter 15 from the first edition has been converted to an appendix. Chapter 6 has been expanded to cover the latest tech­ nology devices. Chapter 1 has been revised, and several examples throughout the book have been revised and updated. But some­ times the more things change, the more they stay the same. All of the guidelines and information presented in this book deal with the three basic testability principles-partitioning, control, and visibility. They have not changed in years. But many people have gotten smarter about how to implement those three basic test­ ability principles, and it is the aim of this text to enlighten the reader regarding those new (and old) testability implementation techniques.

1 Introduction.- How (and Why) Circuits Are Tested.- Key Testability Techniques.- Testability Definitions.- Why Is Testability Important?.- Testability Awareness.- Testability Commitment.- Testability Benefits.- Testability Trends for the Future.- Design-to-Test Overview.- 2 System Level Guidelines.- System Analysis.- System Level Testability Guidelines.- 3 General Digital Circuit Guidelines.- Initialization.- Asynchronous Circuits and One-Shots.- Interfaces.- Built-in Test Diagnostics.- Feedback Loops.- Oscillators and Clocks.- Fan-in and Fan-out Considerations.- Bussed Logic.- Buffers.- Visibility Points.- Partitioning Functions into Logically Separable Units.- Wired OR/AND Functions.- Counters and Shift Registers.- Additional General Digital Board Guidelines.- Guidelines for Programmable Logic Devices.- 4 General Analog Circuit Guidelines.- General Analog Testability Guidelines.- Analog Circuit Elements.- Frequency Considerations.- High-Frequency Analog Circuits 81 Additional General Analog Circuit Guidelines.- Testability Guidelines for Hybrid Circuits.- 5 LSI/VLSI Board Level Guidelines.- LSI/VLSI Board Advantages and Disadvantages.- Partitioning of LSI/VLSI-Based Boards.- Controllability of LSI/VLSI-Based Boards.- Visibility on LSI/VLSI-Based Boards.- Initialization.- Synchronization.- Self-Tests.- Device Standardization.- Summary of LSI/VLSI Board Guidelines.- 6 Merchant Devices on Boards.- General Guidelines Using Merchant Devices.- The 8080A Microprocessor Family.- The 8085A Microprocessor Family.- The 8048 Microprocessor Family.- The 8086 Microprocessor Family.- The 80186 Processor.- The 80286 Processor.- The 80386 Processor.- The Z80 Microprocessor Family.- The Z8000 Microprocessor Family.- The 6800 Microprocessor Family.- The 2901 Microprocessor Family.- The 68000 Processor Family.- The 68020 Processor.- The 68030 Processor.- The 88000 RISC Processor Family.- The 320C2x DSP Device Family.- Merchant Semiconductor Use Guidelines Summary.- 7 LSI/VLSI ASIC Level Techniques.- Level Sensitive Scan Design (LSSD).- Scan Path.- Scan/Set Logic.- Random Access Scan 169 Built-in Logic Block Observation (BILBO).- Signature Analysis.- Reduced Intrusion Scan Path (RISP).- Using Device Scan Paths for Board Level Testing.- Cross Check Technology Embedded Testability.- 8 Boundary Scan.- Board Test Problems as a Basis for Boundary Scan.- Boundary Scan Description.- Test Access Port Description.- Boundary Scan TAP Interconnection and Operation.- Types of Tests Using Boundary Scan.- Boundary Scan Cell Designs.- 9 Built-in Test (BIT) Approaches.- BIT Implementation Requirements.- BIT Access Bus Alternatives.- Chip Level BIT Implementations.- Dual-Port BIT Bus Implementations.- Built-in Test and Human Interactions.- Real-Time On-line Monitoring.- 10 Testability Busses.- The Proposed IEEE Standard Testability Bus.- Testability Busses and LSSD.- Testability Busses and Boundary Scan.- Testability Busses and Scan/Set.- TM and E-TM Testability Busses.- Testability Busses and the TAP.- Real-Time Testability Busses and Multiplexing.- Combination Serial/Real-Time Testability Bus.- Analog Testability Bus Implementation.- Testability Bus Configuration Options.- Testability Busses and ATE.- 11 Mechanical Guidelines.- Overall Test Philosophy.- Accessibility.- Connectors.- Board Layout Guidelines.- Adjustments.- Other Physical Guidelines.- 12 Surface Mount Technology Guidelines.- Mechanical Guidelines for SMT Board Design.- Electrical Guidelines for SMT Board Design.- 13 Software Guidelines.- Hardware Design Factors Required for Software Testability.- General Software Design Guidelines.- Specific Guidelines for Test Control.- Specific Guidelines for Test Modules.- Specific Guidelines for System Level Diagnostics.- Memory Tests.- Specific Guidelines for LRU Testing.- Test Software Development Plans.- 14 Testability Documentation.- Test Software Documentation.- Hardware Documentation.- 15 Implementation Guidelines.- Testability Program Flow.- Design Reviews.- Digital T-Score Rating System and Checklists.- 16 Test Techniques and Strategies.- Production Test Flows.- Cable, Backplane, and Bare Board Continuity Testing.- Loaded Board Opens and Shorts Testing.- In-Circuit Inspection Board Testing.- Manufacturing Defects Testing.- Digital Functional Testing.- Analog PCB Test Equipment.- Combinational Testers.- Choosing a Test Strategy.- Appendix A Testability Checklists.- Appendix B Digital T-Score Rating System.