Design Verification with E

Palnitkar, Samir

ISBN 10: 0131413090 / ISBN 13: 9780131413092

Editore: Prentice Hall, 2003

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Pages can have notes/highlighting. Spine may show signs of wear. ~ ThriftBooks: Read More, Spend Less 0.75. Codice articolo G0131413090I3N00

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Titolo: Design Verification with E

Casa editrice: Prentice Hall

Data di pubblicazione: 2003

Legatura: Paperback

Condizione: Good

Condizione sovraccoperta: No Jacket

Descrizione articolo

Riassunto:

E is a new Hardware Verification Language, or HVL. Verification is one of the most time consuming and cumbersome processes in hardware design. Design teams spend 50% to 70% of their time verifying designs, rather than creating new ones. As designs grow more complex, the verification problems increase exponentially - when a design doubles in size, the verification effort can easily quadruple. In the past design teams have used Verilog and VHDL. E gives engineers the speed and efficiency they have been craving, while also allowing for simulation of other components as well. This book emphasizes breadth rather than depth. It imparts to the reader a working knowledge of a broad variety of e-based topics, thus giving the reader a global understanding of e-based design verification. This book should be classified not only as an e book but, more generally, as a design verification book. Due to its popularity, it is likely that e will be standardized in the future.

Informazioni sull?autore:

About the Author

Samir Palnitkar is the President of Jambo Systems, Inc., a leading ASIC design and verificationservices company and a Verisity Verification Alliance partner. He previously founded IntegratedIntellectual Property, Inc., an ASIC company that was acquired by Lattice Semiconductor, Inc.,and Obongo, Inc., an e-commerce software firm that was acquired by AOL Time Warner, Inc. Heholds a Bachelor of Technology in Electrical Engineering from the Indian Institute ofTechnology, Kanpur; a Master's in Electrical Engineering from the University of Washington,Seattle; and an MBA degree from San Jose State University, San Jose, California. Heis a recognized authority on e , Verilog HDL, modeling, verification, logic synthesis, andEDA-based methodologies in digital design. He has worked extensively with design andverification on various successful microprocessor, ASIC, and system projects; worked on many e -based projects; and trained hundreds of students on e since 1997.