A Designer's Guide to VHDL Synthesis

Thomas J. Wilderotter

ISBN 10: 0792394720 / ISBN 13: 9780792394723

Editore: Springer US, Springer US, 1994

Riguardo questo articolo

Druck auf Anfrage Neuware - Printed after ordering - A Designer's Guide to VHDL Synthesis is intended for both design engineers who want to use VHDL-based logic synthesis ASICs and for managers who need to gain a practical understanding of the issues involved in using this technology. The emphasis is placed more on practical applications of VHDL and synthesis based on actual experiences, rather than on a more theoretical approach to the language. VHDL and logic synthesis tools provide very powerful capabilities for ASIC design, but are also very complex and represent a radical departure from traditional design methods. This situation has made it difficult to get started in using this technology for both designers and management, since a major learning effort and `culture' change is required. A Designer's Guide to VHDL Synthesis has been written to help design engineers and other professionals successfully make the transition to a design methodology based on VHDL and log synthesis instead of the more traditional schematic based approach. While there are a number of texts on the VHDL language and its use in simulation, little has been written from a designer's viewpoint on how to use VHDL and logic synthesis to design real ASIC systems. The material in this book is based on experience gained in successfully using these techniques for ASIC design and relies heavily on realistic examples to demonstrate the principles involved.

Codice articolo 9780792394723

Dati bibliografici

• Titolo: A Designer's Guide to VHDL Synthesis
• Editore: Springer US, Springer US
• Data di pubblicazione: 1994
• Lingua: Inglese
• ISBN 10: 0792394720
• ISBN 13: 9780792394723
• Rilegatura: Buch
• Condizione: Neu
• Dimensioni: 241 L x 160 A x 23 P (millimetri) 241 millimetri di larghezza per 160 millimetri di altezza per 23 millimetri di profondità
• Peso: 676 grammi

Descrizione articolo

Riassunto

A Designer's Guide to VHDL Synthesis is intended for both design engineers who want to use VHDL-based logic synthesis ASICs and for managers who need to gain a practical understanding of the issues involved in using this technology. The emphasis is placed more on practical applications of VHDL and synthesis based on actual experiences, rather than on a more theoretical approach to the language.
VHDL and logic synthesis tools provide very powerful capabilities for ASIC design, but are also very complex and represent a radical departure from traditional design methods. This situation has made it difficult to get started in using this technology for both designers and management, since a major learning effort and `culture' change is required. A Designer's Guide to VHDL Synthesis has been written to help design engineers and other professionals successfully make the transition to a design methodology based on VHDL and log synthesis instead of the more traditional schematic based approach. While there are a number of texts on the VHDL language and its use in simulation, little has been written from a designer's viewpoint on how to use VHDL and logic synthesis to design real ASIC systems. The material in this book is based on experience gained in successfully using these techniques for ASIC design and relies heavily on realistic examples to demonstrate the principles involved.

Contenuti

Preface. 1. Introduction. 2. Making the Transition to VHDL Synthesis. 3. VHDL Background for Synthesis. 4. Synthesis of Sequential Circuits. 5. Sequential Counter Applications. 6. Control Logic and State Machines. 7. Data Processing Functions. 8. Combinational Logic and Optimization. 9. Putting the Pieces Together. 10. Evaluating a Synthesis System. 11. Future Prospects for ASIC Synthesis. Appendix A: Reference Materials. Index.