Digital Timing Macromodeling for VLSI Design Verification
Kong, Jeong-Taek, Overhauser, David V.
ISBN 10: 0792395808 ISBN 13: 9780792395805
Editore: Springer, 1995
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1995. Hardcover. . . . . . Books ship from the US and Ireland. Codice articolo V9780792395805
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Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels.
The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.
Contenuti: List of Figures. List of Tables. Preface. 1. Introduction. 2. Survey of Simulation and Macromodeling Techniques. 3. A Nonlinear Macromodel. 4. Reduction Techniques for Complex Gates. 5. Accounting for RC- Interconnects. 6. Transmission Gate Modeling. 7. Conclusions. A. The SPICE Level 2 Model. B. Nonlinear Macromodel Output Response Derivations. C. The Derivation of M = 0.5 Heuristic in Reduction Techniques. D. Delay Errors for Various AOI Gates. References. Index.
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Titolo: Digital Timing Macromodeling for VLSI Design...
Casa editrice: Springer
Data di pubblicazione: 1995
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Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing)
Editore:
Kluwer Academic Publishers, Norwell, Massachusetts, U.S.A., 1995
ISBN 10: 0792395808
ISBN 13: 9780792395805
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hardcover. Condizione: Very Good. Condizione sovraccoperta: No Dust Jacket. First Edition. White hardcover with white lettering on spine and upper board and contents in very good clean condition, showing minimal signs of wear. Previous owner's name on FEP. Profusely illustrated by diagrams and tables. No dust jacket. T. Used. Codice articolo 249216
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Digital Timing Macromodeling for VLSI Design Verification
Da: Buchpark, Trebbin, Germania
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Condizione: Gut. Zustand: Gut | Sprache: Englisch | Produktart: Bücher. Codice articolo 2297973/3
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Digital Timing Macromodeling for VLSI Design Verification
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Gebunden. Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timi. Codice articolo 5971598
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Digital Timing Macromodeling for VLSI Design Verification (The Springer International Series in Engineering and Computer Science, 319)
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Digital Timing Macromodeling for VLSI Design Verification (The Springer International Series in Engineering and Computer Science, 319)
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Digital Timing Macromodeling for VLSI Design Verification
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Springer US, Springer US Mai 1995, 1995
ISBN 10: 0792395808
ISBN 13: 9780792395805
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Buch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels.The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 292 pp. Englisch. Codice articolo 9780792395805
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Digital Timing Macromodeling for VLSI Design Verification (Hardcover)
Editore:
Kluwer Academic Publishers, Dordrecht, 1995
ISBN 10: 0792395808
ISBN 13: 9780792395805
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Hardcover. Condizione: new. Hardcover. A history of the development of simulation techniques, presenting a detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level and gate-level simulation. The text also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 examines the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodelling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address topics such as: the device model detail; transistor coupling capacitance; effective channel length modulation; series transistor reduction; effective transconductance; input terminal dependence; gate parasitic capacitance; the body effect; the impact of parasitic RC-interconnects; and the effect of transmission gates. Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. Shipping may be from multiple locations in the US or from the UK, depending on stock availability. Codice articolo 9780792395805
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Digital Timing Macromodeling for VLSI Design Verification
Da: AHA-BUCH GmbH, Einbeck, Germania
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Buch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques. Codice articolo 9780792395805
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Digital Timing Macromodeling for VLSI Design Verification
Print on DemandDa: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germania
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Buch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques. 292 pp. Englisch. Codice articolo 9780792395805
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Digital Timing Macromodeling for VLSI Design Verification
Da: Books Puddle, New York, NY, U.S.A.
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Condizione: New. pp. 292 Index. Codice articolo 26319980
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