Direct Transistor-Level Layout for Digital Blocks

Lingua: inglese

Editore: Springer US Mrz 2013, 2013

1475779518 / 9781475779516

Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermaniaBuchWeltWeit Ludwig Meier e.K.

Venditore con 5 stelle

Venditore AbeBooks dal 11 gennaio 2012

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Condizione: Nuovo

EUR 106,99

EUR 23,00 spedizione 
Spedito da Germania a U.S.A.

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Descrizione dell’articolo da parte del venditore

This item is printed on demand - it takes 3-4 days longer - Neuware -Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout.Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers. 140 pp. Englisch.…

Codice articolo 9781475779516

Titolo
Direct Transistor-Level Layout for Digital Blocks
Autore
Rob A. Rutenbar
Editore
Springer US Mrz 2013
Anno di pubblicazione
2013
Condizione
Neu
Rilegatura
Taschenbuch
Lingua
inglese
ISBN 10
1475779518
ISBN 13
9781475779516
Peso dell'articolo
224 grammi
Dimensioni
235x155x8 mm

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Germania

Venditore con 5 stelle

Venditore AbeBooks dal 11 gennaio 2012

Tariffe di spedizione da Germania a U.S.A.

ArticoloDa 5 a 15 giorni lavorativiDa 5 a 15 giorni lavorativi
Primo articoloEUR 23,00EUR 23,00
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BuchWeltWeit Ludwig Meier e.K.

Germania