Embedded Processor-Based Self-Test

Embedded Processor-Based Self-Test is a guide to self-testing strategies for embedded processors. Embedded processors are regularly used today in most System-on-Chips (SoCs). Testing of microprocessors and embedded processors has always been a challenge because most traditional testing techniques fail when applied to them. This is due to the complex sequential structure of processor architectures, which consists of high performance datapath units and sophisticated control logic for performance optimization. Structured Design-for-Testability (DfT) and hardware-based self-testing techniques, which usually have a non-trivial impact on a circuit’s performance, size and power, can not be applied without serious consideration and careful incorporation into the processor design.

Embedded Processor-Based Self-Test shows how the powerful embedded functionality that processors offer can be utilized as a self-testing resource. Through a discussion of different strategies the book emphasizes on the emerging area of Software-Based Self-Testing (SBST). SBST is based on the idea of execution of embedded software programs to perform self-testing of the processor itself and its surrounding blocks in the SoC. SBST is a low-cost strategy in terms of overhead (area, speed, power), development effort and test application cost, as it is applied using low-cost, low-speed test equipment.

Embedded Processor-Based Self-Test can be used by designers, DfT engineers, test practitioners, researchers and students working on digital testing, and in particular processor and SoC test. This book sets the framework for comparisons among different SBST methodologies by discussing key requirements. It presents successful applications of SBST to a number of embedded processors of different complexities and instruction set architectures.

List of Figures. List of Tables. Preface. Acknowledgments. 1. Introduction. 1.1 Book Motivation and Objectives. 1.2 Book Organization. 2. Design Of Processor-Based SOC. 2.1 Integrated Circuits Technology. 2.2 Embedded Core-Based System-on-Chip Design. 2.3 Embedded Processors in SoC Architectures. 3. Testing Of Processor-Based SOC. 3.1 Testing and Design for Testability. 3.2 Hardware-Based Self-Testing. 3.3 Software-Based Self-Testing. 3.4 Software-Based Self-Test and Test Resource Partitioning. 3.5 Why is Embedded Processor Testing Important? 3.6 Why is Embedded Processor Testing Challenging? 4. Processor Testing Techniques. 4.1 Processor Testing Techniques Objectives. 4.1.1 External Testing versus Self-Testing. 4.1.2 DfT-based Testing versus Non-Intrusive Testing. 4.1.3 Functional Testing versus Structural Testing. 4.1.4 Combinational Faults versus Sequential Faults Testing. 4.1.5 Pseudorandom versus Deterministic Testing. 4.1.6 Testing versus Diagnosis. 4.1.7 Manufacturing Testing versus On-line/Field Testing. 4.1.8 Microprocessor versus DSP Testing. 4.2 Processor Testing Literature. 4.2.1 Chronological List of Processor Testing Research. 4.2.2 Industrial Microprocessors Testing. 4.3 Classification of the Processor Testing Methodologies. 5. Software-Based Processor Self-Testing. 5.1 Software-based self-testing concept and flow. 5.2 Software-based self-testing requirements. 5.2.1 Fault coverage and test quality. 5.2.2 Test engineering effort for self-test generation. 5.2.3 Test application time. 5.2.4 A new self-testing efficiency measure. 5.2.5 Embedded memory size for self-test execution. 5.2.6 Knowledge of processor architecture. 5.2.7 Component based self-test code development. 5.3 Software-based self-test methodology overview. 5.4 Processor components classification. 5.4.1 Functional components. 5.4.2 Control components. 5.4.3 Hidden components. 5.5 Processor components test prioritization. 5.5.1 Component size and contribution to fault coverage. 5.5.2 Component accessibility and ease of test. 5.5.3 Components’ testability correlation. 5.6 Component operations identification and selection. 5.7 Operand selection. 5.7.1 Self-test routine development: ATPG. 5.7.2 Self-test routine development: pseudorandom. 5.7.3 Self-test routine development: pre-computed tests. 5.7.4 Self-test routine development: style selection. 5.8 Test development for processor components. 5.8.1 Test development for functional components. 5.8.2 Test development for control components. 5.8.3 Test development for hidden components. 5.9 Test responses compaction in software-based self-testing. 5.10 Optimization of self-test routines. 5.10.1 'Chained' component testing. 5.10.2 'Parallel' component testing. 5.11 Software-based self-testing automation. 6. Case Studies – Experimental Results. 6.1 Parwan processor core. 6.1.1 Software-based self-testing of Parwan. 6.2 Plasma/MIPS processor core. 6.2.1 Software-based self-testing of Plasma/MIPS. 6.3 Meister/MIPS reconfigurable processor core. 6.3.1 Software-based self-testing of Meister/MIPS. 6.4 Jam processor core. 6.4.1 Software-based self-testing of Jam. 6.5 oc8051 microcontroller core. 6.5.1 Software-based self-testing of oc8051. 6.6 RISC-MCU microcontroller core. 6.6.1 Software-based self-testing of RISC-MCU. 6.7 oc54x DSP Core. 6.7.1 Software-based self-testing of oc54x. 6.8 Compaction of test responses. 6.9 Summary of Benchmarks. 7. Processor-Based Testing Of SOC. 7.1 The concept. 7.1.1 Methodology advantages and objectives. 7.2 Literature review. 7.3 Research focus in processor-based SOC testing. 8. Conclusions. References. Index. About the Authors.