Entropy Coders of the H.264/AVC Standard: Algorithms and VLSI Architectures (Signals and Communication Technology)

Tian, Xiaohua; Le, Thinh M.; Lian, Yong

ISBN 10: 364214702X / ISBN 13: 9783642147029

Editore: Springer, 2010

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Codice articolo I-9783642147029

Dati bibliografici

• Titolo: Entropy Coders of the H.264/AVC Standard: Algorithms and VLSI Architectures (Signals and Communication Technology)
• Editore: Springer
• Data di pubblicazione: 2010
• Lingua: Inglese
• ISBN 10: 364214702X
• ISBN 13: 9783642147029
• Rilegatura: Rilegato
• Condizione: New

Descrizione articolo

Riassunto

This book presents a collection of algorithms and VLSI architectures of entropy (or statistical) codecs of recent video compression standards, with focus on the H.264/AVC standard. For any visual data compression scheme, there exists a combination of two, or all of the following three stages: spatial, temporal, and statistical compression. General readers are first introduced with the various algorithms of the statistical coders. The VLSI implementations are also reviewed and discussed. Readers with limited hardware design background are also introduced with a design methodology starting from performance-complexity analyses to software/hardware co-simulation. A typical design of the Contextbased Adaptive Binary Arithmetic Coding (CABAC) encoder is also presented in details. To support System-on-Chip design environment, the CABAC design is wrapped with a SoC-based Wishbone system bus interface.

Dalla quarta di copertina

This book presents a collection of algorithms and VLSI architectures of entropy (or statistical) codecs of recent video compression standards, with focus on the H.264/AVC standard. For any visual data compression scheme, there exists a combination of one, two, or all of the following three stages: spatial, temporal, and statistical compression. General readers are first introduced with the various algorithms of the statistical coders. The VLSI implementations are also reviewed and discussed. Readers with limited hardware design background are also introduced with a design methodology starting from performance-complexity analysis to software/ hardware co-simulation. A typical design of the Context-based Adaptive Binary Arithmetic Coding (CABAC) encoder is also presented in details. To support System-on-Chip design environment, the CABAC design is wrapped with a SoC-based Wishbone system bus interface.