FPGA Implementations of Neural Networks

Jagath C. Rajapakse

ISBN 10: 0387284850 / ISBN 13: 9780387284859

Editore: Springer US, Copernicus, 2006

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Druck auf Anfrage Neuware - Printed after ordering - During the 1980s and early 1990s there was signi cant work in the design and implementation of hardware neurocomputers. Nevertheless, most of these efforts may be judged to have been unsuccessful: at no time have have ha- ware neurocomputers been in wide use. This lack of success may be largely attributed to the fact that earlier work was almost entirely aimed at developing custom neurocomputers, based on ASIC technology, but for such niche - eas this technology was never suf ciently developed or competitive enough to justify large-scale adoption. On the other hand, gate-arrays of the period m- tioned were never large enough nor fast enough for serious arti cial-neur- network (ANN) applications. But technology has now improved: the capacity and performance of current FPGAs are such that they present a much more realistic alternative. Consequently neurocomputers based on FPGAs are now a much more practical proposition than they have been in the past. This book summarizes some work towards this goal and consists of 12 papers that were selected, after review, from a number of submissions. The book is nominally divided into three parts: Chapters 1 through 4 deal with foundational issues; Chapters 5 through 11 deal with a variety of implementations; and Chapter 12 looks at the lessons learned from a large-scale project and also reconsiders design issues in light of current and future technology.

Codice articolo 9780387284859

Dati bibliografici

• Titolo: FPGA Implementations of Neural Networks
• Editore: Springer US, Copernicus
• Data di pubblicazione: 2006
• Lingua: Inglese
• ISBN 10: 0387284850
• ISBN 13: 9780387284859
• Rilegatura: Buch
• Condizione: Neu
• Dimensioni: 241 L x 160 A x 25 P (millimetri) 241 millimetri di larghezza per 160 millimetri di altezza per 25 millimetri di profondità
• Peso: 729 grammi

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Riassunto

During the 1980s and early 1990s there was signi?cant work in the design and implementation of hardware neurocomputers. Nevertheless, most of these efforts may be judged to have been unsuccessful: at no time have have ha- ware neurocomputers been in wide use. This lack of success may be largely attributed to the fact that earlier work was almost entirely aimed at developing custom neurocomputers, based on ASIC technology, but for such niche - eas this technology was never suf?ciently developed or competitive enough to justify large-scale adoption. On the other hand, gate-arrays of the period m- tioned were never large enough nor fast enough for serious arti?cial-neur- network (ANN) applications. But technology has now improved: the capacity and performance of current FPGAs are such that they present a much more realistic alternative. Consequently neurocomputers based on FPGAs are now a much more practical proposition than they have been in the past. This book summarizes some work towards this goal and consists of 12 papers that were selected, after review, from a number of submissions. The book is nominally divided into three parts: Chapters 1 through 4 deal with foundational issues; Chapters 5 through 11 deal with a variety of implementations; and Chapter 12 looks at the lessons learned from a large-scale project and also reconsiders design issues in light of current and future technology.

Contenuti

Preface. 1. FPGA Neurocomputers; A.R.Omondi, J.C.Rajapakse and M.Bajger. 2. Arithmetic precision for BP networks; M.Moussa, S.Areibi and K.Nichols. 3. FPNA: Concepts and properties; B.Girau. 4. FPNA: Applications and implementations; B.Girau. 5. Back-Propagation Algorithms Achieving 5 GOPS on the VirtexE; K.Paul and S.Rajopadhye. 6. FPGA Implementation of Very Large Associative Memories; D.Hammerstrom, C.Gao, S.Zhu and M.Butts. 7. FPGA Implementations of Neocognitrons; A.Noriaki Ide and J.Hiroki Saito. 8. Self Organizing Feature Map for Color Quantization on FPGA; C-H.Chang, M.Shibu and R.Xiao. 9. Implemention of Self-Organizing Feature Maps in Reconfigurable Hardware; M.Porrmann, U.Witkowski and U.Rückert. 10. FPGA Implementation of a Fully and Partially Connected MLP; A.Canas, E.M.Ortigosa, E.Ros and P.M.Ortigosa. 11. FPGA Implementation of Non-Linear Predictors; R.Gadea-Girones and A.Ramrez-Agundis. 12. The REMAP Reconfigurable Architecture: a retrospective; L.Bengtsson, A.Linde, T.Nordstrom, B.Svensson and M.Taveniku.