Riassunto:
This book contains the papers presented at the 13th International Workshop on Field Programmable Logic and Applications (FPL) held on September 1–3, 2003. The conference was hosted by the Institute for Systems and Computer Engineering-Research and Development of Lisbon (INESC-ID) and the Depa- ment of Electrical and Computer Engineering of the IST-Technical University of Lisbon, Portugal. The FPL series of conferences was founded in 1991 at Oxford University (UK), and has been held annually since: in Oxford (3 times), Vienna, Prague, Darmstadt,London,Tallinn,Glasgow,Villach,BelfastandMontpellier.Itbrings together academic researchers, industrial experts, users and newcomers in an - formal,welcomingatmospherethatencouragesproductiveexchangeofideasand knowledge between delegates. Exciting advances in ?eld programmable logic show no sign of slowing down. New grounds have been broken in architectures, design techniques, run-time - con?guration, and applications of ?eld programmable devices in several di?erent areas. Many of these innovations are reported in this volume. The size of FPL conferences has grown signi?cantly over the years. FPL in 2002 saw 214 papers submitted, representing an increase of 83% when compared to the year before. The interest and support for FPL in the programmable logic community continued this year with 216 papers submitted. The technical p- gram was assembled from 90 selected regular papers and 56 posters, resulting in this volume of proceedings. The program also included three invited plenary keynote presentations from LSI Logic, Xilinx and Cadence, and three industrial tutorials from Altera, Mentor Graphics and Dafca.
Contenuti:
Technologies and Trends.- Reconfigurable Circuits Using Hybrid Hall Effect Devices.- Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory.- Communications Applications.- Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture.- Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S.- High Level Design Tools 1.- An Algorithm Designer’s Workbench for Platform FPGAs.- Prototyping for the Concurrent Development of an IEEE 802.11 Wireless LAN Chipset.- Reconfigurable Architectures.- ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix.- Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches.- Arbitrating Instructions in an ??-Coded CCM.- Cryptographic Applications 1.- How Secure Are FPGAs in Cryptographic Applications?.- FPGA Implementations of the RC6 Block Cipher.- Very High Speed 17 Gbps SHACAL Encryption Architecture.- Place and Route Tools.- Track Placement: Orchestrating Routing Structures to Maximize Routability.- Quark Routing.- Global Routing for Lookup-Table Based FPGAs Using Genetic Algorithms.- Multi-context FPGAs.- Virtualizing Hardware with Multi-context Reconfigurable Arrays.- A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device.- Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device.- Cryptographic Applications 2.- Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES.- Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm.- An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers.- Low-Power Issues 1.- Data Processing System with Self-reconfigurable Architecture, for Low Cost, Low Power Applications.- Low Power Coarse-Grained Reconfigurable Instruction Set Processor.- Encoded-Low Swing Technique for Ultra Low Power Interconnect.- Run-Time Configurations.- Building Run-Time Reconfigurable Systems from Tiles.- Exploiting Redundancy to Speedup Reconfiguration of an FPGA.- Run-Time Exchange of Mechatronic Controllers Using Partial Hardware Reconfiguration.- Cryptographic Applications 3.- Efficient Modular-Pipelined AES Implementation in Counter Mode on ALTERA FPGA.- An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm.- Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core.- Compilation Tools.- Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations.- Branch Optimisation Techniques for Hardware Compilation.- A Model for Hardware Realization of Kernel Loops.- Asynchronous Techniques.- Programmable Asynchronous Pipeline Arrays.- Globally Asynchronous Locally Synchronous FPGA Architectures.- Biology-Related Applications.- Case Study of a Functional Genomics Application for an FPGA-Based Coprocessor.- A Smith-Waterman Systolic Cell.- Codesign.- Software Decelerators.- A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer.- Reconfigurable Fabrics.- Extra-dimensional Island-Style FPGAs.- Using Multiplexers for Control and Data in D-Fabrix.- Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics.- Image Processing Applications.- A Real-Time Visualization System for PIV.- A Real-Time Stereo Vision System with FPGA.- Synthesizing on a Reconfigurable Chip an Autonomous Robot Image Processing System.- SAT Techniques.- Reconfigurable Hardware SAT Solvers: A Survey of Systems.- Fault Tolerance Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques.- Hardware Implementations of Real-Time Reconfigurable WSAT Variants.- Application-Specific Architectures.- Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements.- Time and Energy Efficient Matrix Factorization Using FPGAs.- Improving DSP Performance with a Small Amount of Field Programmable Logic.- DSP Applications.- Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA.- An FPGA System for the High Speed Extraction, Normalization and Classification of Moment Descriptors.- Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs.- Dynamic Reconfiguration.- A Self-reconfiguring Platform.- Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices.- Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems.- SoC Architectures.- Networks on Chip as Hardware Components of an OS for Reconfigurable Systems.- A Reconfigurable Platform for Real-Time Embedded Video Image Processing.- Emulation.- Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits.- HW-Driven Emulation with Automatic Interface Generation.- Cache Design.- Implementation of HW$im – A Real-Time Configurable Cache Simulator.- The Bank Nth Chance Replacement Policy for FPGA-Based CAMs.- Arithmetic 1.- Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems.- A New Arithmetic Unit in GF(2 m ) for Reconfigurable Hardware Implementation.- Biologically Inspired Designs.- A Dynamic Routing Algorithm for a Bio-inspired Reconfigurable Circuit.- An FPL Bioinspired Visual Encoding System to Stimulate Cortical Neurons in Real-Time.- Low-Power Issues 2.- Power Analysis of FPGAs: How Practical Is the Attack?.- A Power-Scalable Motion Estimation Architecture for Energy Constrained Applications.- SoC Designs.- A Novel Approach for Architectural Models Characterization. An Example through the Systolic Ring.- A Generic Architecture for Integrated Smart Transducers.- Customisable Core-Based Architectures for Real-Time Motion Estimation on FPGAs.- Cellular Applications.- A High Speed Computation System for 3D FCHC Lattice Gas Model with FPGA.- Implementation of ReCSiP: A ReConfigurable Cell SImulation Platform.- On the Implementation of a Margolus Neighborhood Cellular Automata on FPGA.- Arithmetic 2.- Fast Modular Division for Application in ECC on Reconfigurable Logic.- Non-uniform Segmentation for Hardware Function Evaluation.- A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA.- Fault Analysis.- A Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital Circuits.- Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices.- Fault Simulation Using Partially Reconfigurable Hardware.- Switch Level Fault Emulation.- Network Applications.- An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall.- IPsec-Protected Transport of HDTV over IP.- Fast, Large-Scale String Match for a 10Gbps FPGA-Based Network Intrusion Detection System.- Irregular Reconfigurable CAM Structures for Firewall Applications.- High Level Design Tools 2.- Compiling for the Molen Programming Paradigm.- Laura: Leiden Architecture Research and Exploration Tool.- Communication Costs Driven Design Space Exploration for Reconfigurable Architectures.- From Algorithm Graph Specification to Automatic Synthesis of FPGA Circuit: A Seamless Flow of Graphs Transformations.- Technologies and Trends (Posters).- Adaptive Real-Time Systems and the FPAA.- Challenges and Successes in Space Based Reconfigurable Computing.- Adaptive Processor: A Dynamically Reconfiguration Technology for Stream Processing.- Applications (Posters).- Efficient Reconfigurable Logic Circuits for Matching Complex Network Intrusion Detection Patterns.- FPGAs for High Accuracy Clock Synchronization over Ethernet Networks.- Project of IPv6 Router with FPGA Hardware Accelerator.- A TCP/IP Based Multi-device Programming Circuit.- Tools (Posters).- Design Flow for Efficient FPGA Reconfiguration.- High-Level Design Tools for FPGA-Based Combinatorial Accelerators.- Using System Generator to Design a Reconfigurable Video Encryption System.- MATLAB/Simulink Based Methodology for Rapid-FPGA-Prototyping.- FPGA Implementations (Posters).- DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems.- FPGA Implementation of a Maze Routing Accelerator.- Model Checking Reconfigurable Processor Configurations for Safety Properties.- A Statistical Analysis Tool for FPLD Architectures.- Video and Image Applications (Posters).- FPGA-Implementation of Signal Processing Algorithms for Video Based Industrial Safety Applications.- Configurable Hardware Architecture for Real-Time Window-Based Image Processing.- An FPGA-Based Image Connected Component Labeller.- FPGA Implementation of Adaptive Non-linear Predictors for Video Compression.- Reconfigurable and Low-Power Systems (Posters).- Reconfigurable Systems in Education.- Data Dependent Circuit Design: A Case Study.- Design of a Power Conscious, Customizable CDMA Receiver.- Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms.- Design Techniques (Posters).- A VHDL Library to Analyse Fault Tolerant Techniques.- Hardware Design with a Scripting Language.- Testable Clock Routing Architecture for Field Programmable Gate Arrays.- Neural and Biological Applications (Posters).- FPGA Implementation of Multi-layer Perceptrons for Speech Recognition.- FPGA Based High Density Spiking Neural Network Array.- FPGA-Based Computation of Free-Form Deformations.- FPGA Implementations of Neural Networks – A Survey of a Decade of Progress.- Codesign and Embedded Systems (Posters).- FPGA-Based Hardware/Software CoDesign of an Expert System Shell.- Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System.- Hardware-Software Codesign in Embedded Asymmetric Cryptography Application – A Case Study.- On-chip and Off-chip Real-Time Debugging for Remotely-Accessed Embedded Programmable Systems.- Reconfigurable Systems and Architectures (Posters).- Fast Region Labeling on the Reconfigurable Platform ACE-V.- Modified Fuzzy C-Means Clustering Algorithm for Real-Time Applications.- Reconfigurable Hybrid Architecture for Web Applications.- DSP Applications (Posters).- FPGA Implementation of the Adaptive Lattice Filter.- Specifying Control Logic for DSP Applications in FPGAs.- FPGA Processor for Real-Time Optical Flow Computation.- A Data Acquisition Reconfigurable Coprocessor for Virtual Instrumentation Applications.- Dynamic Reconfiguration (Posters).- Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures.- A Controlled Data-Path Allocation Model for Dynamic Run-Time Reconfiguration of FPGA Devices.- Architecture Template and Design Flow to Support Application Parallelism on Reconfigurable Platforms.- Efficient Implementation of the Singular Value Decomposition on a Reconfigurable System.- Arithmetic (Posters).- A New Reconfigurable-Oriented Method for Canonical Basis Multiplication over a Class of Finite Fields GF(2 m ).- A Study on the Design of Floating-Point Functions in FPGAs.- Design and Implementation of RNS-Based Adaptive Filters.- Domain-Specific Reconfigurable Array for Distributed Arithmetic.- Design and Implementations 1 (Posters).- Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model Checking.- Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler.- Exploiting Stateful Inspection of Network Security in Reconfigurable Hardware.- Propose of a Hardware Implementation for Fingerprint Systems.- Design and Implementations 2 (Posters).- APPLES: A Full Gate-Timing FPGA-Based Hardware Simulator.- Designing, Scheduling, and Allocating Flexible Arithmetic Components.- UNSHADES-1: An Advanced Tool for In-System Run-Time Hardware Debugging.
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