Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing : 10th International Conference, FPL 2000 Villach, Austria, August 27-30, 2000 Proceedings

Reiner W. Hartenstein

ISBN 10: 3540678999 / ISBN 13: 9783540678991

Editore: Springer, Berlin, Springer Berlin Heidelberg, Springer, 2000

Riguardo questo articolo

Neuware - This book is the proceedings volume of the 10th International Conference on Field Programmable Logic and its Applications (FPL), held August 27 30, 2000 in Villach, Austria, which covered areas like reconfigurable logic (RL), reconfigurable computing (RC), and its applications, and all other aspects. Its subtitle 'The Roadmap to Reconfigurable Computing' reminds us, that we are currently witnessing the runaway of a breakthrough. The annual FPL series is the eldest international conference in the world covering configware and all its aspects. It was founded 1991 at Oxford University (UK) and is 2 years older than its two most important competitors usually taking place at Monterey and Napa. FPL has been held at Oxford, Vienna, Prague, Darmstadt, London, Tallinn, and Glasgow (also see: fpl. uni kl. de/FPL/). The New Case for Reconfigurable Platforms: Converging Media. Indicated by palmtops, smart mobile phones, many other portables, and consumer electronics, media such as voice, sound, video, TV, wireless, cable, telephone, and Internet continue to converge. This creates new opportunities and even necessities for reconfigurable platform usage. The new converged media require high volume, flexible, multi purpose, multi standard, low power products adaptable to support evolving standards, emerging new standards, field upgrades, bug fixes, and, to meet the needs of a growing number of different kinds of services offered to zillions of individual subscribers preferring different media mixes.

Codice articolo 9783540678991

Dati bibliografici

• Titolo: Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing : 10th International Conference, FPL 2000 Villach, Austria, August 27-30, 2000 Proceedings
• Editore: Springer, Berlin, Springer Berlin Heidelberg, Springer
• Data di pubblicazione: 2000
• Lingua: Inglese
• ISBN 10: 3540678999
• ISBN 13: 9783540678991
• Rilegatura: Taschenbuch
• Condizione: Neu
• Dimensioni: 233 L x 156 A x 47 P (millimetri) 233 millimetri di larghezza per 156 millimetri di altezza per 47 millimetri di profondità
• Peso: 1301 grammi

Descrizione articolo

Riassunto

This book is the proceedings volume of the 10th International Conference on Field Programmable Logic and its Applications (FPL), held August 27 30, 2000 in Villach, Austria, which covered areas like reconfigurable logic (RL), reconfigurable computing (RC), and its applications, and all other aspects. Its subtitle "The Roadmap to Reconfigurable Computing" reminds us, that we are currently witnessing the runaway of a breakthrough. The annual FPL series is the eldest international conference in the world covering configware and all its aspects. It was founded 1991 at Oxford University (UK) and is 2 years older than its two most important competitors usually taking place at Monterey and Napa. FPL has been held at Oxford, Vienna, Prague, Darmstadt, London, Tallinn, and Glasgow (also see: http://www. fpl. uni kl. de/FPL/). The New Case for Reconfigurable Platforms: Converging Media. Indicated by palmtops, smart mobile phones, many other portables, and consumer electronics, media such as voice, sound, video, TV, wireless, cable, telephone, and Internet continue to converge. This creates new opportunities and even necessities for reconfigurable platform usage. The new converged media require high volume, flexible, multi purpose, multi standard, low power products adaptable to support evolving standards, emerging new standards, field upgrades, bug fixes, and, to meet the needs of a growing number of different kinds of services offered to zillions of individual subscribers preferring different media mixes.

Contenuti

Invited Keynote.- The Rising Wave of Field Programmability.- Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS.- Network Processors.- A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization.- A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors.- Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits.- Internet Connected FPL.- Prototyping.- Field Programmable Communication Emulation and Optimization for Embedded System Design.- FPGA-Based Emulation: Industrial and Custom Prototyping Solutions.- FPGA-Based Prototyping for Product Definition.- Implementation of Virtual Circuits by Means of the FIPSOC Devices.- Dynamically Reconfigurable I.- Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT.- A Self-Reconfigurable Gate Array Architecture.- Multitasking on FPGA Coprocessors.- Design Visualisation for Dynamically Reconfigurable Systems.- Verification of Dynamically Reconfigurable Logic.- Miscellaneous I.- Design of a Fault Tolerant FPGA.- Real-Time Face Detection on a Configurable Hardware System.- Multifunctional Programmable Single-Board CAN Monitoring Module.- Self-Testing of Linear Segments in User-Programmed FPGAs.- Implementing a Fieldbus Interface Using an FPGA.- Technology Mapping and Routing & Placement.- Area-Optimized Technology Mapping for Hybrid FPGAs.- CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs.- Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards.- A Placement Algorithm for FPGA Designs with Multiple I/O Standards.- A Mapping Methodology for Code Trees onto LUT-Based FPGAs.- Biologically Inspired Methods.- Possibilities and Limitations of Applying Evolvable Hardware to Real-World Applications.- A Co-processor System with a Virtex FPGA for Evolutionary Computation.- System Design with Genetic Algorithms.- Implementing Kak Neural Networks on a Reconfigurable Computing Platform.- Compact Spiking Neural Network Implementation in FPGA.- Invited Keynote.- Silicon Platforms for the Next Generation Wireless Systems — What Role Does Reconfigurable Hardware Play?.- Invited Papers.- From Reconfigurability to Evolution in Construction Systems: Spanning the Electronic, Microfluidic and Biomolecular Domains.- A Specific Test Methodology for Symmetric SRAM-Based FPGAs.- Mobile Communication.- DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communication Applications.- Fast Carrier and Phase Synchronization Units for Digital Receivers Based on Re-configurable Logic.- Software Radio Reconfigurable Hardware System (SHaRe).- Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform.- Dynamically Reconfigurable II.- Partial Run-Time Reconfiguration Using JRTR.- A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems.- A Hybrid Prototyping Platform for Dynamically Reconfigurable Designs.- Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer.- Design Space Exploration.- Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures.- Mapping of DSP Algorithms on Field Programmable Function Arrays.- On Availability of Bit-Narrow Operations in General-Purpose Applications.- A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers.- A New Floorplanning Method for FPGA Architectural Research.- Miscellaneous II.- Efficient Self-Reconfigurable Implementations Using On-chip Memory.- Design and Implementation of an XC6216 FPGA Model in Verilog.- Reusable DSP Functions in FPGAs.- A Parallel Pipelined SAT Solver for FPGA’s.- A Multi-node Dynamic Reconfigurable Computing System with Distributed Reconfiguration Controller.- Applications I.- A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems.- A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System.- Reconfigurable Computing for Speech Recognition: Preliminary Findings.- Security Upgrade of Existing ISDN Devices by Using Reconfigurable Logic.- The Fastest Multiplier on FPGAs with Redundant Binary Representation.- Optimization.- High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs.- Balancing Logic Utilization and Area Efficiency in FPGAs.- Performance Penalty for Fault Tolerance in Roving STARs.- Optimum Functional Decomposition for LUT-Based FPGA Synthesis.- Optimization of Run-Time Reconfigurable Embedded Systems.- Invited Keynote.- It’s FPL, Jim — But Not as We Know It! Opportunities for the New Commercial Architectures.- Invited Paper.- Reconfigurable Systems: New Activities in Asia.- StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox.- Architectures.- Stream Computations Organized for Reconfigurable Execution (SCORE).- Memory Access Schemes for Configurable Processors.- Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory.- Combining Serialisation and Reconfiguration for FPGA Designs.- Methodology and Technology.- Multiple-Wordlength Resource Binding.- Automatic Temporal Floorplanning with Guaranteed Solution Feasibility.- A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology.- Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPGAs.- Compilation and Related Issues.- Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware.- Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis.- Behavioural Language Compilation with Virtual Hardware Management.- Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs.- Applications II.- Evaluation of Accelerator Designs for Subgraph Isomorphism Problem.- The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware.- Multiplexer Based Reconfiguration for Virtex Multipliers.- Efficient Building of Word Recognizer in FPGAs for Term-Document Matrices Construction.- Short Papers.- Reconfigurable Computing between Classifications and Metrics — The Approach of Space/Time-Scheduling.- FPGA Implementation of a Prototype WDM On-Line Scheduler.- An FPGA Based Scheduling Coprocessor for Dynamic Priority Scheduling in Hard Real-Time Systems.- Formal Verification of a Reconfigurable Microprocessor.- The Role of the Embedded Memories in the Implementation of Artificial Neural Networks.- Programmable System Level Integration Brings System-on-Chip Design to the Desktop.- On Applying Software Development Best Practice to FPGAs in Safety-Critical Systems.- Pre-route Assistant: A Routing Tool for Run-Time Reconfiguration.- High Speed Computation of Lattice Gas Automata with FPGA.- An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture.- FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers.- Toward Uniform Approach to Design of Evolvable Hardware Based Systems.- Educational Programmable Hardware Prototyping and Verification System.- A Stream Processor Architecture Based on the Con.gurable CEPRA-S.- An Innovative Approach to Couple EDA Tools with Recon.gurable Hardware.- FPL Curriculum at Tallinn Technical University.- The Modular Architecture of SYNTHUP, FPGA Based PCI Board for Real-Time Sound Synthesis and Digital Signal Processing.- A Rapid Prototyping Environment for Microprocessor Based System-on-Chips and Its Application to the Development of a Network Processor.- Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers.- Wireless Base Station Design Using a Reconfigurable Communications Processor.- Placement of Linear Arrays.