This state-of-the-art monograph presents a coherent survey of a variety of methods and systems for formal hardware verification. It emphasizes the presentation of approaches that have matured into tools and systems usable for the actual verification of nontrivial circuits. All in all, the book is a representative and well-structured survey on the success and future potential of formal methods in proving the correctness of circuits. The various chapters describe the respective approaches supplying theoretical foundations as well as taking into account the application viewpoint. By applying all methods and systems presented to the same set of IFIP WG10.5 hardware verification examples, a valuable and fair analysis of the strenghts and weaknesses of the various approaches is given.

Contenuti:

Symbolic trajectory evaluation.- Automated verification with abstract state machines using multiway decision graphs.- Design verification using Synchronized Transitions.- Hardware verification using PVS.- Verifying VHDL designs with COSPAN.- The C@S system: Combining proof strategies for system verification.- Appendix: The common book examples.

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