Formal Semantics and Proof Techniques for Optimizing VHDL Models

Kothanda Umamageswaran

ISBN 10: 146137331X / ISBN 13: 9781461373315

Editore: Springer US, Springer New York Okt 2012, 2012

Riguardo questo articolo

This item is printed on demand - Print on Demand Titel. Neuware -Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions.Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 184 pp. Englisch.

Codice articolo 9781461373315

Dati bibliografici

• Titolo: Formal Semantics and Proof Techniques for Optimizing VHDL Models
• Editore: Springer US, Springer New York Okt 2012
• Data di pubblicazione: 2012
• Lingua: Inglese
• ISBN 10: 146137331X
• ISBN 13: 9781461373315
• Rilegatura: Taschenbuch
• Condizione: Neu
• Dimensioni: 235 L x 155 A x 11 P (millimetri) 235 millimetri di larghezza per 155 millimetri di altezza per 11 millimetri di profondità
• Peso: 289 grammi

Descrizione articolo

Riassunto

Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions.
Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.

Contenuti

1. Introduction. 2. Related Work. 3. The Static Model. 4. A Well-Formed VHDL Model. 5. The Reduction Algebra. 6. Completeness of the Reduced Form. 7. Interval Temporal Logic. 8. The Dynamic Model. 9. Applications of the Dynamic Model. 10. A Framework for Proving Equivalences Using PVS. 11. Conclusions. Appendices. References. Index.