Hardware Architectures for Post-Quantum Digital Signature Schemes

Deepraj Soni

ISBN 10: 3030576817 / ISBN 13: 9783030576813

Editore: Springer International Publishing, Springer International Publishing, 2020

Riguardo questo articolo

Druck auf Anfrage Neuware - Printed after ordering - This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs.Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based;Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms;Enables designers to build hardware implementations that are resilient to a variety of side-channels.

Codice articolo 9783030576813

Dati bibliografici

• Titolo: Hardware Architectures for Post-Quantum Digital Signature Schemes
• Editore: Springer International Publishing, Springer International Publishing
• Data di pubblicazione: 2020
• Lingua: Inglese
• ISBN 10: 3030576817
• ISBN 13: 9783030576813
• Rilegatura: Buch
• Condizione: Neu
• Dimensioni: 241 L x 160 A x 17 P (millimetri) 241 millimetri di larghezza per 160 millimetri di altezza per 17 millimetri di profondità
• Peso: 459 grammi

Descrizione articolo

Riassunto

This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification.  The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs.

• Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based;
• Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms;
• Enables designers to build hardware implementations that are resilient to a variety of side-channels.

Informazioni sull?autore

Deepraj Soni is a Ph.D. student at NYU Tandon School of Engineering. Deepraj works on hardware implementation, evaluation and security of post quantum cryptographic algorithms. He received his M.Tech from the Department of Electrical Engineering, Indian Institute of Technology Bombay (IIT B). His thesis focused on developing a framework for hardware software co simulator and neural network implementation on an FPGA. After graduation, Deepraj worked as a design engineer in the semiconductor division of Samsung and SanDisk. At Samsung, he was responsible for the design and architecture of the image processing IPs such as region segmentation and Embedded CODEC. He was also responsible for communication IPs such as FFT/IFFT, Time & Frequency Deinterleaving and Demapper for canceling the noise. At SanDisk, Deepraj helped in the development of System On Chip (SoC) level design for the memory controller.