Hardware Support for Efficient Transactional Memory Systems: Hardware Techniques for High-Performance Transactional Memory in Many-Core Chip Multiprocessors

Titos-Gil, Ruben

ISBN 10: 3847336525 / ISBN 13: 9783847336525

Editore: LAP LAMBERT Academic Publishing, 2012

Riguardo questo articolo

Like New.

Codice articolo ERICA79638473365256

Dati bibliografici

• Titolo: Hardware Support for Efficient Transactional Memory Systems: Hardware Techniques for High-Performance Transactional Memory in Many-Core Chip Multiprocessors
• Editore: LAP LAMBERT Academic Publishing
• Data di pubblicazione: 2012
• Lingua: Inglese
• ISBN 10: 3847336525
• ISBN 13: 9783847336525
• Rilegatura: Paperback
• Condizione: Like New
• Tipo di libro: book

Descrizione articolo

Riassunto

The rise of multicores has brought the problem of effective concurrent programming to the forefront of computing research, presenting both immense opportunities and enormous challenges. Traditional multithreaded programming models use low-level primitives such as locks to guarantee mutual exclusion and protect shared data. The trade-off between programming ease and performance imposed by locks remains one of the key challenges to programmers and computer architects of the multicore era. Transactional Memory (TM) is a conceptually simpler programming model that can help boost developer productivity by eliminating the complex task of reasoning about the intricacies of safe fine-grained locking. Fast implementations of transactional programming constructs are necessary for TM to gain widespread usage. This book focuses on the hardware mechanisms that provide optimistic concurrency control with stringent guarantees of atomicity and isolation, with the intent of achieving high-performance across a variety of workloads, at a reasonable cost in terms of design complexity.

L'autore

Dr. Ruben Titos-Gil is a post-doc researcher at the Chalmers University of Technology in Sweden. He earned a PhD Degree from the University of Murcia, Spain. His research interests include parallel computer architecture and programming models. He is the author of several articles published in reputed conferences and journals.