High Frequency Interconnect Characterization and Modeling : For VLSI On-Chip Interconnects and RF Package Wire Bonds

Xiaoning Qi

ISBN 10: 3639130952 / ISBN 13: 9783639130959

Editore: VDM Verlag Dr. Müller, 2009

Riguardo questo articolo

nach der Bestellung gedruckt Neuware - Printed after ordering - Continuous scaling of transistors combined withincreased chip area results in the ratio of globalwire delay to gate delay increasing at a super-linearrate. Simple RC models have become inadequate forsimulation of VLSI circuits. In addition, parasiticinductance and capacitance of IC packages imposelimits on the circuit performance at RF frequencies.This book presents modeling of on-chip inductance forchips with ground grids that emulate those used inreal circuits. S-parameter characterization of testchips up to 10 GHz shows good agreement withsimulation and analytical calculations. On-chip 3-Dcapacitance modeling capabilities for arbitrarilyshaped objects are also presented. In addition, anapproach to fast 3-D modeling of the geometry forbonding wires in RF circuits and packages isdemonstrated. The geometry and an equivalent circuitare presented to model the frequency response ofbonding wires. Excellent agreement between modeledresults and measured data is achieved for frequenciesup to 10 GHz. The book should be useful to thesemiconductor professionals in academia and industry,who are interested in the on-chip and packageinterconnects researches.

Codice articolo 9783639130959

Dati bibliografici

• Titolo: High Frequency Interconnect Characterization and Modeling : For VLSI On-Chip Interconnects and RF Package Wire Bonds
• Editore: VDM Verlag Dr. Müller
• Data di pubblicazione: 2009
• Lingua: Inglese
• ISBN 10: 3639130952
• ISBN 13: 9783639130959
• Rilegatura: Taschenbuch
• Condizione: Neu
• Dimensioni: 220 L x 150 A x 8 P (millimetri) 220 millimetri di larghezza per 150 millimetri di altezza per 8 millimetri di profondità
• Peso: 193 grammi

Descrizione articolo

Riassunto

Continuous scaling of transistors combined with increased chip area results in the ratio of global wire delay to gate delay increasing at a super-linear rate. Simple RC models have become inadequate for simulation of VLSI circuits. In addition, parasitic inductance and capacitance of IC packages impose limits on the circuit performance at RF frequencies. This book presents modeling of on-chip inductance for chips with ground grids that emulate those used in real circuits. S-parameter characterization of test chips up to 10 GHz shows good agreement with simulation and analytical calculations. On-chip 3-D capacitance modeling capabilities for arbitrarily shaped objects are also presented. In addition, an approach to fast 3-D modeling of the geometry for bonding wires in RF circuits and packages is demonstrated. The geometry and an equivalent circuit are presented to model the frequency response of bonding wires. Excellent agreement between modeled results and measured data is achieved for frequencies up to 10 GHz. The book should be useful to the semiconductor professionals in academia and industry, who are interested in the on-chip and package interconnects researches.

L'autore

Xiaoning Qi, Ph.D.: Studied Electrical Engineering at Stanford University. Senior Staff Engineer at Intel Corp. on signal and power integrity for semiconductor systems. He worked on power integrity for high speed I/O, process variation, leakage currents, on-chip interconnects and CAD tools at Rambus, Synopsys and Sun Microsystems, California.