High-Level Power Analysis and Optimization

Dey Sujit Jha Niraj K. Raghunathan Anand

ISBN 10: 1461374812 / ISBN 13: 9781461374817

Editore: Springer, 2012

Riguardo questo articolo

Print on Demand pp. 156 66:B&W 7 x 10 in or 254 x 178 mm Perfect Bound on White w/Gloss Lam.

Codice articolo 55079906

Dati bibliografici

• Titolo: High-Level Power Analysis and Optimization
• Editore: Springer
• Data di pubblicazione: 2012
• Lingua: Inglese
• ISBN 10: 1461374812
• ISBN 13: 9781461374817
• Rilegatura: Brossura
• Condizione: New

Descrizione articolo

Riassunto

High-Level Power Analysis and Optimization presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behavior) levels of the design hierarchy, which are often the levels that yield the most power savings. This book describes power estimation and optimization techniques for use during high-level (behavioral synthesis), as well as for designs expressed at the register-transfer or architecture level.
High-Level Power Analysis and Optimization surveys the state-of-the-art research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power.
High-Level Power Analysis and Optimization will be very useful reading for students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies.

Contenuti

List of Figures. List of Tables. Preface. 1. Introduction. 2. Background. 3. Architecture-Level Power Estimation. 4. Power Management. 5. High-Level Synthesis for Low Power. 6. Conclusions and Future Work. References. Index.