High Level Synthesis of ASICs under Timing and Synchronization Constraints

Ku, David C.; de Micheli, Giovanni

ISBN 10: 0792392442 / ISBN 13: 9780792392446

Editore: Kluwer Academic Publishers, Boston, 1992

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Name from previous owner on FEP. Light surface wear to covers and slightly softened corners, though otherwise binding is very well preserved. Pages are clean and crisp, and printing is tight, clean and bright throughout. No Dust Jacket. MB.

Codice articolo 248464

Dati bibliografici

• Titolo: High Level Synthesis of ASICs under Timing and Synchronization Constraints
• Editore: Kluwer Academic Publishers, Boston
• Data di pubblicazione: 1992
• Lingua: Inglese
• ISBN 10: 0792392442
• ISBN 13: 9780792392446
• Rilegatura: hardcover
• Condizione: Very Good
• Condizione della sovraccoperta: No Dust Jacket
• Tipo di libro: Used
• Cataloghi dei venditori:
  • Science - Electronics

Descrizione articolo

Riassunto

Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers.
High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book.
Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model.
The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.

Contenuti

1. Introduction. 2. System Overview. 3. Behavioral Transformations. 4. Sequencing Graph and Resource Model. 5. Design Space Exploration. 6. Relative Scheduling. 7. Resource Conflict Resolution. 8. Relative Control Generation. 9. Relative Control Optimization. 10. System Implementation. 11. Experimental Results. 12. Conclusions and Future Work. References. Index.