High Performance Clock Distribution Networks: Springer; Reprinted from THE JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS, Vol. 16 No. 2 & 3 (1997)

Friedman, Eby G. (editor)

ISBN 10: 0792399676 / ISBN 13: 9780792399674

Editore: Kluwer Academic Publishers, 1997

Riguardo questo articolo

Kluwer, 1997. Slim hardback, no dustjacket. 276pp. Minor wear to covers, name to inside back cover. Good.

Codice articolo 13615418

Dati bibliografici

• Titolo: High Performance Clock Distribution Networks: Springer; Reprinted from THE JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS, Vol. 16 No. 2 & 3 (1997)
• Editore: Kluwer Academic Publishers
• Data di pubblicazione: 1997
• Lingua: Inglese
• ISBN 10: 0792399676
• ISBN 13: 9780792399674
• Rilegatura: Hardcover
• Edizione: seconda edizione
• Condizione: Good
• Condizione della sovraccoperta: No Jacket
• Tipo di libro: Book
• Cataloghi dei venditori:
  • Rare
  • Computing
  • Essays

Descrizione articolo

Riassunto

Ten articles reprinted from the Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology vol. 16 (1997) explore advanced aspects of clock signals used to synchronize the movement of data within semiconductor systems. They discuss exploiting the localized nature of clock skew, the implementation of clock distribution networks, and long-range aspects of the next generation of such networks. The specific topics include optimizing clock skew for peak current reductions, buffered clock tree synthesis with non-zero clock skew scheduling for an increased tolerance to process parameter variations, useful-skew clock routing in gate sizing for low-power design, practical bounded-skew clock routing, a clock methodology for high-performance microprocessors, optimal clock distribution in electronic systems, and the timing of multi-gigahertz rapid single-flux quantum digital circuits. No index. Annotation c. by Book News, Inc., Portland, Or.

Contenuti

Introduction; E.G. Friedman. Clock Skew Optimization for Peak Current Reduction; L. Benini, et al. Clocking Optimization and Distribution in Digital Systems with Scheduled Skews; Hong-Yean Hsieh, et al. Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations; J.L. Neves, E.G. Friedman. Useful-Skew Clock Routing with Gate Sizing for Low Power Design; J.G. Xi, W. W.-M. Dai. Clock Distribution Methodology for PowerPCTM Microprocessors; S. Ganguly, et al. Circuit Placement, Chip Optimization, and Wire Routing for IBM IC Technology; D.J. Hathaway, et al. Practical Bounded-Skew Clock Routing; A. Kahng, C.-W. A. Tsao. A Clock Methodology for High-Performance Microprocessors; K.M. Carrig, et al. Optical Clock Distribution in Electronic Systems; S.K. Tewksbury, L.A. Hornak. Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits; K. Gaj, et al.