Hot-Carrier Reliability of MOS VLSI Circuits (Paperback)

Yusuf Leblebici

ISBN 10: 1461364299 / ISBN 13: 9781461364290

Editore: Springer-Verlag New York Inc., New York, NY, 2012

Riguardo questo articolo

Paperback. As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. Shipping may be from multiple locations in the US or from the UK, depending on stock availability.

Codice articolo 9781461364290

Dati bibliografici

• Titolo: Hot-Carrier Reliability of MOS VLSI Circuits (Paperback)
• Editore: Springer-Verlag New York Inc., New York, NY
• Data di pubblicazione: 2012
• Lingua: Inglese
• ISBN 10: 1461364299
• ISBN 13: 9781461364290
• Rilegatura: Paperback
• Condizione: new

Descrizione articolo

Riassunto

As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada­ tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down­ ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation.

Contenuti

Preface. 1. Introduction. 2. Oxide Degradation Mechanisms in MOS Transistors. 3. Modeling of Degradation Mechanisms. 4. Modeling of Damaged MOSFETs. 5. Transistor-Level Simulation for Circuit Reliability. 6. Fast Timing Simulation for Circuit Reliability. 7. Macromodeling of Hot-Carrier Induced Degradation in MOS Circuits. 8. Circuit Design for Reliability. Index.