Hybrid Code-Based Test Data Compression and Decompression for VLSI Circuits

Kalamani Chinnappa Gounder

ISBN 10: 3668737509 ISBN 13: 9783668737501
Editore: GRIN Verlag, 2018
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Hybrid Code-Based Test Data Compression and Decompression for VLSI Circuits | Kalamani Chinnappa Gounder | Taschenbuch | 216 S. | Englisch | 2018 | GRIN Verlag | EAN 9783668737501 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu. Codice articolo 114129961

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Doctoral Thesis / Dissertation from the year 2018 in the subject Computer Science - Applied, grade: 6, Anna University, course: PhD, language: English, abstract: Test data compression is an effective method for reducing test data volume and memory requirement with relatively small cost. An effective test structure for embedded hard cores is easy to implement and it is also capable of producing high-quality tests as part of the design flow. The purpose of Test data compression intends to reduce Test data volume by using Test Stimulus Compression such as Code-based schemes, Linear-decompression-based schemes and Broadcast-scan-based schemes. The research work addresses the problem of the test data volume and memory requirements. The primary objective of this study is to introduce novel techniques that improve the compression ratio by reducing test data volume during at-speed test in scan designs. This in turn diminishes the tester memory requirement and hence chip area is reduced for Built-in-Self Test environment. The aim of this research is to introduce various compression algorithms by combining the existing data compression techniques. The algorithms are designed to reduce the volume of test patterns of input that is essential to guarantee an acceptable level of fault coverage which is a key parameter to evaluate the quality of testing.

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Titolo: Hybrid Code-Based Test Data Compression and ...
Casa editrice: GRIN Verlag
Data di pubblicazione: 2018
Legatura: Taschenbuch
Condizione: Neu

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Kalamani Chinnappa Gounder
Editore: GRIN Verlag, 2018
ISBN 10: 3668737509 ISBN 13: 9783668737501
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Taschenbuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - Doctoral Thesis / Dissertation from the year 2018 in the subject Computer Science - Applied, grade: 6, Anna University, course: PhD, language: English, abstract: Test data compression is an effective method for reducing test data volume and memory requirement with relatively small cost. An effective test structure for embedded hard cores is easy to implement and it is also capable of producing high-quality tests as part of the design flow.The purpose of Test data compression intends to reduce Test data volume by using Test Stimulus Compression such as Code-based schemes, Linear-decompression-based schemes and Broadcast-scan-based schemes.The research work addresses the problem of the test data volume and memory requirements. The primary objective of this study is to introduce novel techniques that improve the compression ratio by reducing test data volume during at-speed test in scan designs. This in turn diminishes the tester memory requirement and hence chip area is reduced for Built-in-Self Test environment.The aim of this research is to introduce various compression algorithms by combining the existing data compression techniques. The algorithms are designed to reduce the volume of test patterns of input that is essential to guarantee an acceptable level of fault coverage which is a key parameter to evaluate the quality of testing. Codice articolo 9783668737501

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Kalamani Chinnappa Gounder
Editore: GRIN Verlag Jul 2018, 2018
ISBN 10: 3668737509 ISBN 13: 9783668737501
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Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Doctoral Thesis / Dissertation from the year 2018 in the subject Computer Science - Applied, grade: 6, Anna University, course: PhD, language: English, abstract: Test data compression is an effective method for reducing test data volume and memory requirement with relatively small cost. An effective test structure for embedded hard cores is easy to implement and it is also capable of producing high-quality tests as part of the design flow.The purpose of Test data compression intends to reduce Test data volume by using Test Stimulus Compression such as Code-based schemes, Linear-decompression-based schemes and Broadcast-scan-based schemes.The research work addresses the problem of the test data volume and memory requirements. The primary objective of this study is to introduce novel techniques that improve the compression ratio by reducing test data volume during at-speed test in scan designs. This in turn diminishes the tester memory requirement and hence chip area is reduced for Built-in-Self Test environment.The aim of this research is to introduce various compression algorithms by combining the existing data compression techniques. The algorithms are designed to reduce the volume of test patterns of input that is essential to guarantee an acceptable level of fault coverage which is a key parameter to evaluate the quality of testing. 216 pp. Englisch. Codice articolo 9783668737501

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Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Doctoral Thesis / Dissertation from the year 2018 in the subject Computer Science - Applied, grade: 6, Anna University, course: PhD, language: English, abstract: Test data compression is an effective method for reducing test data volume and memory requirement with relatively small cost. An effective test structure for embedded hard cores is easy to implement and it is also capable of producing high-quality tests as part of the design flow. The purpose of Test data compression intends to reduce Test data volume by using Test Stimulus Compression such as Code-based schemes, Linear-decompression-based schemes and Broadcast-scan-based schemes. The research work addresses the problem of the test data volume and memory requirements. The primary objective of this study is to introduce novel techniques that improve the compression ratio by reducing test data volume during at-speed test in scan designs. This in turn diminishes the tester memory requirement and hence chip area is reduced for Built-in-Self Test environment. The aim of this research is to introduce various compression algorithms by combining the existing data compression techniques. The algorithms are designed to reduce the volume of test patterns of input that is essential to guarantee an acceptable level of fault coverage which is a key parameter to evaluate the quality of testing.Books on Demand GmbH, Überseering 33, 22297 Hamburg 216 pp. Englisch. Codice articolo 9783668737501

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