IDDQ Testing of VLSI Circuits. Questo articolo non è disponibile.IDDQ Testing of VLSI Circuits

Power supply current monitoring to detect CMOS IC defects during production testing quietly laid down its roots in the mid-1970s. Both Sandia Labs and RCA in the United States and Philips Labs in the Netherlands practised this procedure on their CMOS ICs. At that time, this practice stemmed simply from an intuitive sense that CMOS ICs showing abnormal quiescent power supply current (I-DDQ) contained defects. Later, this intuition was supported by data and analysis in the 1980s by Levi (RACD), Malaiya and Su (SUNY-Binghamton), Soden and Hawkins (Sandia Labs and the University of New Mexico), Jacomino and co-workers (Laboratoire d'Automatique de Grenoble), and maly and co-workers (Carnegie Mellon University). Interest in I-DDQ testing has advanced beyond the data reported in the 1980s and is now focused on applications and evaluations involving larger volumes of ICs that improve quality beyond what can be achieved by previous conventional means. In the conventional style of testing one attempts to propagate the logic states of the suspended nodes to primary outputs. This is done for all or most nodes of the circuit. For sequential circuits, in particular, the complexity of finding suitable tests is very high. In comparison, the I-DDQ test does not observe the logic states, but measures the integrated current that leaks through all gates. In other words, it is like measuring a patient's temperature to determine the state of health. Despite perceived advantages, during the years that followed its initial announcements, scepticism about the practicality of I-DDQ testing prevailed. The idea, however, provided a great opportunity to researchers. New results on test generation, fault simulation, design for testability, built-in self-test, and diagnosis for this style of testing have since been reported.

IDDQ Testing: A Review.- Iddq Testing as a Component of a Test Suite: The Need for Several Fault Coverage Metrics.- Iddq Testing in CMOS Digital ASICs.- Reliability Benefits of IDDQ.- Quiescent Current Analysis and Experimentation of Defective CMOS Circuits.- QUIETEST: A Methodology for Selecting IDDQ Test Vectors.- Generation and Evaluation of Current and Logic Tests for Switch-Level Sequential Circuits.- Diagnosis of Leakage Faults with IDDQ.- Algorithms for IDDQ Measurement Based Diagnosis of Bridging Faults.- Proportional BIC Sensor for Current Testing.- Design of ICs Applying Built-in Current Testing.