Integrated Circuit Defect-Sensitivity: Theory and Computational Models (Paperback)

Jose Pineda de Gyvez

ISBN 10: 1461363837 / ISBN 13: 9781461363835

Editore: Springer-Verlag New York Inc., New York, NY, 2014

Riguardo questo articolo

Paperback. The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology-and design-laboratories. For years the "silicon foundry" concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Those fabrication plants would be concentrated with only a few market leaders. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Shipping may be from our Sydney, NSW warehouse or from our UK or US warehouse, depending on stock availability.

Codice articolo 9781461363835

Dati bibliografici

• Titolo: Integrated Circuit Defect-Sensitivity: Theory and Computational Models (Paperback)
• Editore: Springer-Verlag New York Inc., New York, NY
• Data di pubblicazione: 2014
• Lingua: Inglese
• ISBN 10: 1461363837
• ISBN 13: 9781461363835
• Rilegatura: Paperback
• Condizione: new

Descrizione articolo

Riassunto

The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology-and design-laboratories. For years the "silicon foundry" concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Those fabrication plants would be concentrated with only a few market leaders.

Contenuti

Foreword. Preface. 1. Introduction. 2. Defect Semantics and Yield Modeling. 3. Computational Models for Defect-Sensitivity. 4. Single Defect Multiple Layer. 5. Fault Analysis and Multiple Layer Critical Areas. 6. Single Defect Single Layer (SDSL) Model. 7. IC Yield Prediction and Single Layer Critical Areas. 8. Single vs. Multiple Layer Critical Areas. References. Appendix 1: Sources of Defect Mechanisms. Appendix 2: End Effects of Critical Regions. Appendix 3: NMOS Technology File. Index.