Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 16th International Workshop, PATMOS 2006, Montpellier, . (Lecture Notes in Computer Science)

ISBN 10: 3540390944 / ISBN 13: 9783540390947

Editore: Springer Berlin Heidelberg, 2006

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Dati bibliografici

• Titolo: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 16th International Workshop, PATMOS 2006, Montpellier, . (Lecture Notes in Computer Science)
• Editore: Springer Berlin Heidelberg
• Data di pubblicazione: 2006
• Lingua: Inglese
• ISBN 10: 3540390944
• ISBN 13: 9783540390947
• Rilegatura: Paperback
• Condizione: Like New
• Tipo di libro: book

Descrizione articolo

Riassunto

This book constitutes the refereed proceedings of the 16th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2006. The book presents 41 revised full papers and 23 revised poster papers together with 4 key notes and 3 industrial abstracts. Topical sections include high-level design, power estimation and modeling memory and register files, low-power digital circuits, busses and interconnects, low-power techniques, applications and SoC design, modeling, and more.

Contenuti

Session 1 – High-Level Design.- Design of Parallel Implementations by Means of Abstract Dynamic Critical Path Based Profiling of Complex Sequential Algorithms.- Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism.- Handheld System Energy Reduction by OS-Driven Refresh.- Session 2 – Power Estimation / Modeling.- Delay Constrained Register Transfer Level Dynamic Power Estimation.- Circuit Design Style for Energy Efficiency: LSDL and Compound Domino.- Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage.- Leakage Power Characterization Considering Process Variations.- Session 3 – Memory and Register Files.- Heuristic for Two-Level Cache Hierarchy Exploration Considering Energy Consumption and Performance.- System Level Multi-bank Main Memory Configuration for Energy Reduction.- SRAM CP: A Charge Recycling Design Schema for SRAM.- Compiler-Driven Leakage Energy Reduction in Banked Register Files.- Session 4 – Low-Power Digital Circuits.- Impact of Array Data Flow Analysis on the Design of Energy-Efficient Circuits.- Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations.- Low-Power Adaptive Bias Amplifier for a Large Supply-Range Linear Voltage Regulator.- Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design.- Session 5 – Busses and Interconnects.- Power Modeling of a NoC Based Design for High Speed Telecommunication Systems.- Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance.- Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology.- Two Efficient Synchronous Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures.- Session 6 – Low Power Techniques.- Low-Power Maximum Magnitude Computation for PAPR Reduction in OFDM Transmitters.- Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.- A Clock Generator Driven by a Unified-CBiCMOS Buffer Driver for High Speed and Low Energy Operation.- Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique.- Session 7 – Applications and SoC Design.- Low Power Distance Measurement Unit for Real-Time Hardware Motion Estimators.- Reducing Energy Dissipation of Wireless Sensor Processors Using Silent-Store-Filtering MoteCache.- A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus.- Methodology for Dynamic Power Verification of Contactless Smartcards.- New Battery Status Checking Method for Implantable Biomedical Applications.- Session 8 – Modeling.- Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis.- A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique.- Zephyr: A Static Timing Analyzer Integrated in a Trans-hierarchical Refinement Design Flow.- Receiver Modeling for Static Functional Crosstalk Analysis.- Modeling of Crosstalk Fault in Defective Interconnects.- Session 9 – Digital Circuits.- Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits.- Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations.- IR-drop Reduction Through Combinational Circuit Partitioning.- Low-Power Register File Based on Adiabatic Logic Circuits.- High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI.- Session 10 – Reconfigurable and Programmable Devices.- Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources.- An FPGA Power Aware Design Flow.- The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing.- Poster 1.- Optimization of Master-Slave Flip-Flops for High-Performance Applications.- Hierarchical Modeling of a Fractional Phase Locked Loop.- Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs.- Statistical Characterization of Library Timing Performance.- Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors.- Low Clock Swing D Flip-Flops Design by Using Output Control and MTCMOS.- Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations.- Worst Case Crosstalk Noise Effect Analysis in DSM Circuits by ABCD Modeling.- Poster 2.- A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors.- Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications.- Spectral Analysis of the On-Chip Waveforms to Generate Guidelines for EMC-Aware Design.- A Scalable Power Modeling Approach for Embedded Memory Using LIB Format.- Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors.- A CMOS Compatible Charge Recovery Logic Family for Low Supply Voltages.- A Framework for Estimating Peak Power in Gate-Level Circuits.- Poster 3.- QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis.- Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm.- Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry.- A Novel Methodology to Reduce Leakage Power in CMOS Complementary Circuits.- Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis.- Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks.- A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits.- Keynotes.- Nanoelectronics: Challenges and Opportunities.- Static and Dynamic Power Reduction by Architecture Selection.- Asynchronous Design for High-Speed and Low-Power Circuits.- Design for Volume Manufacturing in the Deep Submicron ERA.- Industrial Session.- The Holy Grail of Holistic Low-Power Design.- Top Verification of Low Power System with “Checkerboard” Approach.- The Power Forward Initiative.