Integrated Circuit and System Design : Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, Patmos 2004, Santorini, Greece, September 15-17, 2004, Proceedings

Macii, Enrico (EDT); Paliouras, Vassilis (EDT); Koufopavlou, Odysseas (EDT)

ISBN 10: 3540230955 / ISBN 13: 9783540230953

Editore: Springer, 2004

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Dati bibliografici

• Titolo: Integrated Circuit and System Design : Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, Patmos 2004, Santorini, Greece, September 15-17, 2004, Proceedings
• Editore: Springer
• Data di pubblicazione: 2004
• Lingua: Inglese
• ISBN 10: 3540230955
• ISBN 13: 9783540230953
• Rilegatura: Brossura
• Condizione: New

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Riassunto

WelcometotheproceedingsofPATMOS2004,thefourteenthinaseriesofint- national workshops. PATMOS 2004 was organized by the University of Patras with technical co-sponsorship from the IEEE Circuits and Systems Society. Over the years, the PATMOS meeting has evolved into an important - ropean event, where industry and academia meet to discuss power and timing aspects in modern integrated circuit and system design. PATMOS provides a forum for researchers to discuss and investigate the emerging challenges in - sign methodologies and tools required to develop the upcoming generations of integrated circuits and systems. We realized this vision this year by providing a technical program that contained state-of-the-art technical contributions, a keynote speech, three invited talks and two embedded tutorials. The technical program focused on timing, performance and power consumption, as well as architectural aspects, with particular emphasis on modelling, design, charac- rization, analysis and optimization in the nanometer era. This year a record 152 contributions were received to be considered for p- sible presentation at PATMOS. Despite the choice for an intense three-day m- ting, only 51 lecture papers and 34 poster papers could be accommodated in the single-track technical program. The Technical Program Committee, with the - sistance of additional expert reviewers, selected the 85 papers to be presented at PATMOS and organized them into 13 technical sessions. As was the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were received per manuscript.

Contenuti

Keynote Speech.- Connecting E-Dreams to Deep-Submicron Realities.- Invited Talks.- Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization.- Low-Voltage Embedded RAMs – Current Status and Future Trends.- Adaptive Subthreshold Leakage Reduction Through N/P Wells Reverse Biasing.- Embedded Tutorials.- Leakage in CMOS Circuits – An Introduction.- The Certainty of Uncertainty: Randomness in Nanometer Design.- Session 1: Buses and Communication.- Crosstalk Cancellation for Realistic PCB Buses.- A Low-Power Encoding Scheme for GigaByte Video Interfaces.- Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures.- Perfect 3-Limited-Weight Code for Low Power I/O.- A High-Level DSM Bus Model for Accurate Exploration of Transmission Behaviour and Power Estimation of Global System Buses.- Session 2: Circuits and Devices (I).- Performance Metric Based Optimization Protocol.- Temperature Dependence in Low Power CMOS UDSM Process.- Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques.- High Yield Standard Cell Libraries: Optimization and Modeling.- A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits.- Session 3: Low Power (I).- Sleepy Stack Reduction of Leakage Power.- A Cycle-Accurate Energy Estimator for CMOS Digital Circuits.- Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures.- Reducing Cross-Talk Induced Power Consumption and Delay.- Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell.- Leakage Power Analysis and Comparison of Deep Submicron Logic Gates.- Session 4: Architectures.- Threshold Mean Larger Ratio Motion Estimation in MPEG Encoding Using LNS.- Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless Applications.- Register Isolation for Synthesizable Register Files.- Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures.- Design of High-Speed Low-Power Parallel-Prefix VLSI Adders.- Session 5: Asynchronous Circuits.- GALSification of IEEE 802.11a Baseband Processor.- TAST Profiler and Low Energy Asynchronous Design Methodology.- Low Latency Synchronization Through Speculation.- Minimizing the Power Consumption of an Asynchronous Multiplier.- A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling.- Session 6: System Design.- L0 Cluster Synthesis and Operation Shuffling.- On Combined DVS and Processor Evaluation.- A Multi-level Validation Methodology for Wireless Network Applications.- SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level.- Run-Time Software Monitor of the Power Consumption of Wireless Network Interface Cards.- Towards a Software Power Cost Analysis Framework Using Colored Petri Net.- Session 7: Circuits and Devices (II).- A 260ps Quasi-static ALU in 90nm CMOS.- Embedded EEPROM Speed Optimization Using System Power Supply Resources.- Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption.- A Predictive Synchronizer for Periodic Clock Domains.- Power Supply Net for Adiabatic Circuits.- Session 8: Interconnect and Physical Design.- A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI.- Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.- An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design.- Wirelength Reduction Using 3-D Physical Design.- On Skin Effect in On-Chip Interconnects.- Session 9: Security and Safety.- A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits.- A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors.- A Flexible and Accurate Energy Model of an Instruction-Set Simulator for Secure Smart Card Software Design.- The Impact of Low-Power Techniques on the Design of Portable Safety-Critical Systems.- Session 10: Low Power (II).- Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems.- PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures.- Power Consumption of Performance-Scaled SIMD Processors.- Low Effort, High Accuracy Network-on-Chip Power Macro Modeling.- Exploiting Dynamic Workload Variation in Offline Low Energy Voltage Scheduling.- Session 11: Low-Power Processing (Poster).- Design of a Power/Performance Efficient Single-Loop Sigma-Delta Modulator for Wireless Receivers.- Power Aware Dividers in FPGA.- A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses.- The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms.- Low Power Co-design Tool and Power Optimization of Schedules and Memory System.- Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform.- Enhancing GALS Processor Performance Using Data Classification Based on Data Latency.- Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors.- Power Modeling, Estimation, and Optimization for Automated Co-design of Real-Time Embedded Systems.- Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path.- Power Estimation for Ripple-Carry Adders with Correlated Input Data.- LPVIP: A Low-Power ROM-Less ALU for Low-Precision LNS.- Session 12: Digital Design (Poster).- Low Level Adaptive Frequency in Synthesis of High Speed Digital Circuits.- A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic.- Pipelines in Dynamic Dual-Rail Circuits.- Optimum Buffer Size for Dynamic Voltage Processors.- Design Optimization with Automated Cell Generation.- A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool.- A Novel Constant-Time Fault-Secure Binary Counter.- Buffer Sizing for Crosstalk Induced Delay Uncertainty.- Optimal Logarithmic Representation in Terms of SNR Behavior.- A New Logic Transformation Method for Both Low Power and High Testability.- Energy-Efficient Hardware Architecture for Variable N-point 1D DCT.- Session 13: Modeling and Simulation (Poster).- Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits.- A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment.- Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis.- On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects.- Signal Sampling Based Transition Modeling for Digital Gates Characterization.- Physical Extension of the Logical Effort Model.- An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies.- Moment-Based Estimation of Switching Activity for Correlated Distributions.- Table-Based Total Power Consumption Estimation of Memory Arrays for Architects.- A Physically Oriented Model to Quantify the Noise-on-Delay Effect.- Noise Margin in Low Power SRAM Cells.- Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic.