Integrating Functional and Temporal Domains in Logic Design | The False Path Problem and Its Implications

Patrick C. McGeer (u. a.)

ISBN 10: 1461367689 / ISBN 13: 9781461367680

Editore: Springer, 2012

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Integrating Functional and Temporal Domains in Logic Design | The False Path Problem and Its Implications | Patrick C. McGeer (u. a.) | Taschenbuch | xxiii | Englisch | 2012 | Springer | EAN 9781461367680 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.

Codice articolo 105720936

Dati bibliografici

• Titolo: Integrating Functional and Temporal Domains in Logic Design | The False Path Problem and Its Implications
• Editore: Springer
• Data di pubblicazione: 2012
• Lingua: Inglese
• ISBN 10: 1461367689
• ISBN 13: 9781461367680
• Rilegatura: Taschenbuch
• Condizione: Neu
• Dimensioni: 235 L x 155 A x 14 P (millimetri) 235 millimetri di larghezza per 155 millimetri di altezza per 14 millimetri di profondità
• Peso: 371 grammi
• Cataloghi dei venditori:
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Descrizione articolo

Riassunto

This book is an extension of one author's doctoral thesis on the false path problem. The work was begun with the idea of systematizing the various solutions to the false path problem that had been proposed in the literature, with a view to determining the computational expense of each versus the gain in accuracy. However, it became clear that some of the proposed approaches in the literature were wrong in that they under­ estimated the critical delay of some circuits under reasonable conditions. Further, some other approaches were vague and so of questionable accu­ racy. The focus of the research therefore shifted to establishing a theory (the viability theory) and algorithms which could be guaranteed correct, and then using this theory to justify (or not) existing approaches. Our quest was successful enough to justify presenting the full details in a book. After it was discovered that some existing approaches were wrong, it became apparent that the root of the difficulties lay in the attempts to balance computational efficiency and accuracy by separating the tempo­ ral and logical (or functional) behaviour of combinational circuits. This separation is the fruit of several unstated assumptions; first, that one can ignore the logical relationships of wires in a network when considering timing behaviour, and, second, that one can ignore timing considerations when attempting to discover the values of wires in a circuit.

Contenuti

1 Introduction.- 1.1 Timing Analysis of Circuits.- 1.1.1 Delay Models.- 1.1.2 Graph Theory Formulation.- 1.2 The General False Path Problem.- 1.2.1 Explicit Recording of False Paths.- 1.2.2 Case Analysis.- 1.2.3 Directionality Tags on Pass Transistors.- 1.2.4 Automated Solutions.- 1.3 A Note on Notation.- 1.3.1 On “Implications”.- 1.3.2 A Final Word on Notation.- 1.4 Logic Notation.- 1.4.1 Cubes.- 1.4.2 Cofactors.- 1.4.3 A Family of Operators.- 1.5 Outline.- 2 The False Path Problem.- 2.1 Introduction.- 2.2 Dynamic Timing Analysis.- 2.3 Viable Paths.- 2.4 Symmetric Networks and Monotonicity.- 2.5 Viability Under Network Transformations.- 2.6 The Viability Function.- 2.7 Summary.- 3 False Path Detection Algorithms.- 3.1 Generic False Path Detection Algorithm.- 3.1.1 Depth-First Search.- 3.1.2 Best-First Search.- 3.1.3 Generic Procedure.- 3.1.4 Modifying the Generic Procedure to find Every Long True Path.- 3.1.5 Varying Input Times, Output Times, and Slacks.- 3.1.6 Separate Rise and Fall Delays.- 3.1.7 Don’t-Care Conditions.- 3.2 Viability Analysis Procedure.- 3.2.1 Naive Depth-First Search Procedure.- 3.2.2 Dynamic Programming Procedure.- 3.3 Dynamic Programming Algorithm Example.- 3.4 Finding all the Longest Viable Paths.- 3.5 Recent Work.- 4 System Considerations and Approximations.- 4.1 Approximation Theory and Practice.- 4.2 “Weak” Viability.- 4.3 The Brand-Iyengar Procedure.- 4.4 The Du-Yen-Ghanta Criteria.- 4.5 The Chen-Du Criterion.- 4.6 More Macroexpansion Transformations.- 4.7 Biased Satisfiability Tests.- 4.8 Axes of Approximation.- 4.9 The Lllama Timing Environment.- 4.10 Experimental Results.- 5 Hazard Prevention in Combinational Circuits.- 5.1 Introduction.- 5.2 Hazards.- 5.3 The Boolean n-Space.- 5.4 The SDC Set and Restricted Cubes.- 5.5 Ordering The Inputs.- 6 Timing Analysis in Hazard-Free Networks.- 6.1 Introduction.- 6.2 Robustness of Dynamic Sensitization.- 6.3 The Dynamic Sensitization Function.- 6.4 Algorithms.- 6.5 Conclusion.- A Complexity Results.- A.1 An Introduction to Polynomial Reducibility.- B A Family of Operators.- C Fast Procedures for Computing Dataflow Sets.- C.1 Introduction.- C.2 Terminology.- C.3 The New Approach.- C.4 Computations.- C.4.1 Basic Algorithms.- C.4.2 Transitivity.- C.4.4 Evaluation Algorithms.- C.5 Correctness.- C.6 Complexity Analysis.- C.7 Efficiency.- C.8 Sparse Matrix Implementation.- C.9 An Improvement.- C.10 Results.- C.11 Extensions.- C.11.1 Extending Arbitrary Cubes.- C.11.2 The Fanout Care Set and the Test Function.- D Precharged, Unate Circuits.