Interconnect Technology and Design for Gigascale Integration

. Ed(s): Davis, Jeffrey A. (College of Computing, Georgia Institute of Technology, Atlanta, USA); Meindl, James D.

ISBN 10: 1402076061 / ISBN 13: 9781402076060

Editore: Kluwer Academic Publishers, 2003

Riguardo questo articolo

Includes topics ranging from IBM's revolutionary copper process to an exploration into interconnect-aware computer architectures. Editor(s): Davis, Jeffrey A. (College of Computing, Georgia Institute of Technology, Atlanta, USA); Meindl, James D. Num Pages: 411 pages, biography. BIC Classification: TJFC; TJFD. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 23. Weight in Grams: 779. . 2003. Hardback. . . . . Books ship from the US and Ireland.

Codice articolo V9781402076060

Dati bibliografici

• Titolo: Interconnect Technology and Design for Gigascale Integration
• Editore: Kluwer Academic Publishers
• Data di pubblicazione: 2003
• Lingua: Inglese
• ISBN 10: 1402076061
• ISBN 13: 9781402076060
• Rilegatura: Rilegato
• Condizione: New

Descrizione articolo

Riassunto

This book is jointly authored by leading academic and industry researchers. The material is unique in that it spans IC interconnect topics ranging from IBM's revolutionary copper process to an in-depth exploration into interconnect-aware computer architectures.

Contenuti

1. Interconnect Opportunities for GSI.- 1.1 Introduction.- 1.2 The Interconnect Problem.- 1.3 Reverse Scaling.- 1.4 System-on-Chip.- 1.5 Three-Dimensional Integration.- 1.6 Input/Output Interconnect Enhancements.- 1.7 Photonic Interconnects.- 1.8 Conclusions.- 2. Copper BEOL Interconnects for Silicon CMOS Logic Technology.- 2.1 Introduction.- 2.2 BEOL Evolution.- 2.3 The Case for Copper.- 2.4 Electroplating of Cu.- 2.5 Reliability of Cu Interconnects.- 2.6 Processing of Cu Interconnects.- 2.7 Summary.- 3. Interconnect Parasitic Extraction of Resistance, Capacitance, and Inductance.- 3.1 Introduction.- 3.2 Electromagnetic Formulation.- 3.3 Resistance Extraction.- 3.4 Capacitance Extraction.- 3.5 Inductance Extraction.- 3.6 Summary.- 4. Distributed RC and RLC Transient Models.- 4.1 Introduction.- 4.2 Distributed RC Models.- 4.3 Distributed RLC Models.- 4.4 Non-Ideal Return Paths.- 4.5 Summary.- 5. Power, Clock, and Global Signal Distribution.- 5.1 Introduction.- 5.2 Global Signal Interconnect Modeling.- 5.3 Global Clock Distribution Modeling.- 5.4 Global Power Distribution Modeling.- 5.5 An Integrated Architecture for Global Interconnects.- 5.6 Conclusions.- 6. Stochastic Multilevel Interconnect Modeling and Optimization.- 6.1 Introduction.- 6.2 Wire-Length Distribution Model.- 6.3 Net Model Approximation.- 6.4 Comparisons with Actual Data.- 6.5 Critical Path Model.- 6.6 Dynamic Power Dissipation Model.- 6.7 Optimal n-Tier Multilevel Interconnect Architectures.- 6.8 Summary.- 7. Interconnect-Centric Computer Architectures.- 7.1 Introduction and Motivation.- 7.2 Interconnect-Aware Architectures.- 7.3 Interconnect Demand Models.- 7.4 Related Work.- 7.5 GENESYS Organization and Models.- 7.6 Heterogeneous Architecture Models.- 7.7 System Design Analysis.- 7.8 Wire Demands and their Relation to Architecture.- 7.9 Conclusion.- 8. Chip-to-Module Interconnect.- 8.1 Introduction.- 8.2 Packaging and Chip-to-Module Trends.- 8.3 Microvia Printed Wiring Board Technologies.- 8.4 Chip-to-Module Interconnections for GSI.- 9. 3-D ICs DSM Interconnect Performance Modeling and Analysis.- 9.1 Introduction.- 9.2 Motivation for 3-D ICs.- 9.3 Scope of This Study.- 9.4 Area and Performance Estimation of 3-D ICs.- 9.5 Challenges for 3-D ICs.- 9.6 mplications for Circuit Design and System-on-a-Chip Applications.- 9.7 Overview of 3-D IC Technology.- 9.8 Conclusions.- 10. Silicon Microphotonics.- 10.1 Introduction.- 10.2 Optical Interconnection.- 10.3 Monolithic Silicon Microphotonics.- 10.4 Optical Clock Distribution and Data I/O.- 10.5 Summary.