Logic Synthesis for Low Power VLSI Designs

Massoud Pedram

ISBN 10: 1461374901 / ISBN 13: 9781461374909

Editore: Springer US, Springer New York Okt 2012, 2012

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This item is printed on demand - Print on Demand Titel. Neuware -Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 256 pp. Englisch.

Codice articolo 9781461374909

Dati bibliografici

• Titolo: Logic Synthesis for Low Power VLSI Designs
• Editore: Springer US, Springer New York Okt 2012
• Data di pubblicazione: 2012
• Lingua: Inglese
• ISBN 10: 1461374901
• ISBN 13: 9781461374909
• Rilegatura: Taschenbuch
• Condizione: Neu
• Dimensioni: 235 L x 155 A x 15 P (millimetri) 235 millimetri di larghezza per 155 millimetri di altezza per 15 millimetri di profondità
• Peso: 394 grammi

Descrizione articolo

Riassunto

Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.
Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.

Contenuti

Preface. I: Background, Terminology, and Power Modeling. 1. Introduction. 2. Technology Independent Power Analysis and Modeling. II: Two-Level Function Optimization for Low Power. 3. Two-Level Logic Minimization in CMOS Circuits. 4. Two-Level Logic Minimization in PLAs. III: Multi-Level Network Optimization for Low Power. 5. Logic Restructuring for Low Power. 6. Logic Minimization for Low Power. 7. Technology Dependent Optimization for Low Power; Chi-ying Tsui. 8. Post Mapping Structural Optimization for Low Power. IV: Power Optimization Methodology. 9. POSE: Power Optimization and Synthesis Environment: (http://atrak.usc.edu/~pose) V: Conclusion. 10. Concluding Remarks. Index.