Numerical Validation in Current Hardware Architectures

ISBN 10: 3642015905 / ISBN 13: 9783642015908

Editore: Springer, 2009

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pp. 276.

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Dati bibliografici

• Titolo: Numerical Validation in Current Hardware Architectures
• Editore: Springer
• Data di pubblicazione: 2009
• Lingua: Inglese
• ISBN 10: 3642015905
• ISBN 13: 9783642015908
• Rilegatura: Brossura
• Condizione: New

Descrizione articolo

Riassunto

The major emphasis of the Dagstuhl Seminar on Numerical Validation in C- rent Hardware Architectures lay on numerical validation in current hardware architecturesand softwareenvironments. The generalidea wasto bring together experts who are concerned with computer arithmetic in systems with actual processor architectures and scientists who develop, use, and need techniques from veri?ed computation in their applications. Topics of the seminar therefore included: The ongoing revision of the IEEE 754/854 standard for ?oating-point ari- metic Feasible ways to implement multiple precision (multiword) arithmetic and to compute the actual precision at run-time according to the needs of input data The achievement of a similar behavior of ?xed-point, ?oating-point and - terval arithmetic across language compliant implementations The design of robust and e?cient numerical programsportable from diverse computers to those that adhere to the IEEE standard The development and propagation of validated special-purpose software in di?erent application areas Error analysis in several contexts Certi?cation of numerical programs, veri?cation and validation assessment Computer arithmetic plays an important role at the hardware and software level, when microprocessors, embedded systems, or grids are designed. The re- ability of numerical softwarestrongly depends on the compliance with the cor- sponding ?oating-point norms. Standard CISC processors follow the 1985 IEEE norm 754, which is currently under revision, but the new highly performing CELL processor is not fully IEEE compliant.

Dalla quarta di copertina

This book constitutes the thoroughly refereed post-proceedings of the Dagstuhl Seminar 08021 on Numerical Validation in Current Hardware Architectures held at Dagstuhl Castle, Germany, in January 2008.

The 16 revised full papers presented were selected during two rounds of reviewing and improvements. The papers are organized in topical sections on languages, software systems and tools, new verification techniques based on interval arithmetic, applications in science and engineering, and novel approaches to verification.