PCI Express* Electrical Interconnect Design

Peters, Stephen,Kolbehdari, Mohammad,Gardiner, Scott,Coleman, David

ISBN 10: 0974364991 / ISBN 13: 9780974364995

Editore: Intel Pr, 2004

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Dati bibliografici

• Titolo: PCI Express* Electrical Interconnect Design
• Editore: Intel Pr
• Data di pubblicazione: 2004
• Lingua: Inglese
• ISBN 10: 0974364991
• ISBN 13: 9780974364995
• Rilegatura: Paperback
• Condizione: Good

Descrizione articolo

Riassunto

Written for system design engineers, board and layout designers, signal integrity engineers, designers of high-speed communications devices, test engineers and technicians and validation engineers, this practical guide explains this products' serial architecture that offers scalable bandwidth and features that meet next-generation systems. It covers signal integrity design modeling, time domain analysis, frequency domain analysis, system layout and printed circuit board design, add-in card modules, design validation, and measurement techniques. Annotation ©2004 Book News, Inc., Portland, OR (booknews.com)

Contenuti

iii
Contents
Acknowledgments ix
Chapter 1 PCI Express† Electrical Architecture 1
Electrical Advantages and Built-in Capabilities 3
Signal Performance 3
Clocking 7
Electromagnetic Compatibility 8
AC Coupling 11
Ports, Links, and Lanes 11
Link Training 12
Detect 12
Data Rate Negotiation 13
Polarity Inversion 14
Lane-to-Lane De-skew 14
Lane Number and Width Negotiation 16
Lane Reversal 17
PCI Express† Electrical Specifications 18
Topology and Interconnect Overview 18
A Paradigm Shift 20
Signal Integrity Essentials 21
iv PCI Express† Electrical Interconnect Design
Chapter 2 Signal Integrity Design Modeling 33
Component Loss-based Method 33
PCI Express† Interconnect Simulation Models 34
Package and Circuit Characterization 35
FCBGA and WB-BGA Package Types 35
Package and Die Validation Model 39
Driver Model 40
IBIS Model 41
On-die Decoupling Capacitance 42
Receiver Model 42
PCB Modeling 42
PCB Interconnect Model 43
W-element and N-element Models 45
Signal Integrity Phenomena 49
Loss 50
Crosstalk 52
Reflections 54
AC Coupling Capacitance 55
PCB Vias Model 55
Connectors 57
Die-to-Die Simulation Model 57
Time Domain Simulation Model 57
Frequency Domain Simulation Model 58
Power Delivery Network 59
Power Delivery Analysis 59
PDN Drivers 60
PDN Time Domain Design Parameters 60
PDN Frequency Domain Design Parameters 60
PDN Modeling 61
Driver and On-die Capacitance 62
Package and PCB Models 62
Decoupling Capacitor Model 62
Vias and Socket Model 62
Power Supply Model 63
PDN Simulation Method 63
Simplified PDN Model 64
Contents v
Chapter 3 Time Domain Analysis 65
Voltage Modes 66
Mode Conversion 66
Transmitter Parameters 67
Receiver Parameters 69
Excitation Pattern 71
ISI Pattern 72
Crosstalk Pattern 72
SSO Pattern 74
Data Bit-Stream Length 74
DOE Analysis 74
DOE Input Parameters 75
Order of Curve Fitting 76
Drive Inputs 76
Interconnect Inputs 77
Receiver Parameters 77
DOE Example 77
Margin Mode Computation 82
Eye Measuring 82
System Model and Add-in Card Topologies 85
Eye Diagram and Compliance Jitter 86
Driver and Receiver Eye Requirements 86
Driver and Receiver Simulation Topology 88
Chapter 4 Frequency Domain Analysis 89
Single-ended and Differential S-parameters 90
Frequency Domain Interconnect Model 93
Parameters of Measurement and Simulation 93
Multi-pair Aggressor-Victim Model 93
Excitation Matrix 95
Differential Mode Voltage 96
Common Mode Voltages 97
Impedance Mismatch 98
Multi-segment Topology and the ABCD Method 99
Chain or ABCD Matrix Method 99
S-parameters Versus ABCD Matrix 100
S-parameters of the Cascaded Multi-segment 101
S-parameters with Load and Source 102
vi PCI Express† Electrical Interconnect Design
Mason’s Rule 103
Loss Budget Partitioning 104
Correlation Between Frequency and Time Domains 105
Differential Insertion Loss 105
Common Mode Losses 106
Chapter 5 Successful System Layout Design—
Getting Started 107
System Topology Overviews 108
Taking Advantage of the PCI Express† Specification 112
Connectivity Rules 112
Bowtie Topology Considerations 114
System-level Floor-planning 117
Routing Length Recommendations and Restrictions 118
System Reference Clock Considerations 120
AC Coupling Capacitors 124
Cable Considerations for System Design 128
ExpressCard† Internal Cable Interface 129
Riser and Daughter Card Implementations 132
PCI Express† Extension Risers 132
Daughter Cards for ExpressCard† Modules 134
Other System Design Considerations: Power Delivery, Thermal and
Acoustical Management, and EMI 136
Power Delivery 136
Thermal and Acoustical Management 140
EMI Mitigation 142
Chapter 6 Printed Circuit Board Design
Considerations 143
PCB Stackup Configurations and Tradeoffs 143
General Effects of a PCB Stackup on Electrical Performance 144
Four-layer Stackups: Microstrip Trace Designs 145
Multi-layer Stackups: Stripline Trace Designs 149
High-Speed Trace Routing 153
Differential Pairs: Impedance and Routing 153
Differential Pairs: Width and Spacing 155
Differential Pair Routing Lengths 159
Length Matching—When and Where? 160
Contents vii
Reference Planes 162
Bends 164
Breakout Areas 168
Via Usage and Placement 172
Chapter 7 Add-in Cards and ExpressCard† Modules 175
Form Factor Requirements 175
Add-in Card Form Factors 176
Add-in Card Interoperability 177
ExpressCard† Form Factors and Interoperability 179
Connectors 184
Add-in Card Connectors 184
ExpressCard† Connectors 189
Edgefinger and PCB Design 191
Edgefinger and Mating Interface Design Guidelines 192
PCB Design Guidelines for Add-in Cards and ExpressCard†
Modules 194
Reference Clock Considerations and Requirements 196
Cable Considerations 197
Additional Design Considerations for Power Delivery,
Thermal/Acoustical Management, and EMI 198
Add-in Card Power Delivery Guidelines 198
ExpressCard† Power Delivery Guidelines 200
Add-in Card Thermal and Acoustic Management 201
ExpressCard† Thermal and Acoustic Management 204
EMI Considerations for Add-in Cards and Modules 205
Chapter 8 Validating the Design 207
Real-Time Versus Equivalent-Time Sampling Scopes 208
Real-Time Sampling Scopes 208
Equivalent-Time Sampling Scopes 209
Minimum Bandwidth Requirements 210
Effects of Probe Capacitance 214
Simulating the Effects of Bandwidth Limits and Probe Loading 215
Scope Noise Floor and Gain Errors 216
Differential versus Single-ended Probing 217
Understanding the AC and DC Specifications 218
viii PCI Express† Electrical Interconnect Design
Understanding the Tx and Rx Eye Diagrams 219
The Unit Interval 219
Transmitter Eye Diagram 220
Receiver Eye Diagram 221
The Eye at the Add-in Card Connector 223
DC Common Mode Voltage 223
AC Common Mode Voltage 224
Rise and Fall Times 226
Lane-to-Lane Skew 227
Transmitter Lane Skew 227
Lane-to-Lane Skew at the Receiver 228
Common Mode and Differential Impedance 229
Understanding Bit Error Rate (BER) 231
Measuring BER 232
Chapter 9 Measurement Techniques 235
Stimulus for Data Acquisition 235
Compliance Measurement Mode (CMM) 236
Loopback 238
Using Loopback in Electrical Validation of a Link 239
Oscilloscope Calibration and Probe De-skew 240
Oscilloscope Self-Calibration (OSC) 240
DC Calibration 241
Probe De-skew 244
Using Coax Cables as Oscilloscope Probes 247
Test Platform 247
Measurement Acquisition 249
Data Acquisition at the Transmitter 251
Data Acquisition at the Receiver 253
Data Post-Processing and Analysis 255
Measuring PCI Express† Version 1.1 Compliance 256
Layout Rules for Probes and SMA Connectors 257
Building Good SMA Footprints 257
Probing Points and Layout Rules for Scope Landing Pads 260
References 263
Index 265