Power-Constrained Testing of VLSI Circuits

Bashir M. Al-Hashimi

ISBN 10: 140207235X / ISBN 13: 9781402072352

Editore: Springer US, Springer US Feb 2003, 2003

Riguardo questo articolo

This item is printed on demand - Print on Demand Titel. Neuware -Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 192 pp. Englisch.

Codice articolo 9781402072352

Dati bibliografici

• Titolo: Power-Constrained Testing of VLSI Circuits
• Editore: Springer US, Springer US Feb 2003
• Data di pubblicazione: 2003
• Lingua: Inglese
• ISBN 10: 140207235X
• ISBN 13: 9781402072352
• Rilegatura: Buch
• Condizione: Neu
• Dimensioni: 241 L x 160 A x 16 P (millimetri) 241 millimetri di larghezza per 160 millimetri di altezza per 16 millimetri di profondità
• Peso: 459 grammi

Descrizione articolo

Riassunto

This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths.

Contenuti

1: Design and Test of Digital Integrated Circuits. 1.1. Introduction. 1.2. VLSI Design Flow. 1.3. External Testing Using Automatic Test Equipment. 1.4. Internal Testing Using Built-in Self-Test. 1.5. Power Dissipation During Test Application. 1.6. Organization of the Book. 2: Power Dissipation During Test. 2.1. Introduction. 2.2. Test Power Modeling and Preliminaries. 2.3. Power Concerns During Test. 2.4. Sources of Higher Power Dissipation During Test Application. 2.5. Summary. 3: Approaches to Handle Test Power. 3.1. Introduction. 3.2. A Taxonomy of the Existing Approaches for Power-Constrained Testing. 3.3. Test Set Dependent vs. Test Set Independent Approaches. 3.4. Test-per-Clock vs. Test-per-Scan. 3.5. Internal Test vs. External Test. 3.6. Single vs. Multiple Test Sources and Sinks. 3.7. Power-Constrained Test Scheduling. 3.8. Summary. 4: Best Primary Input Change Time. 4.1. Introduction. 4.2. Scan Cell and Test Vector Reordering. 4.3. Technique for Power Minimization. 4.4. Algorithms for Power Minimization. 4.5. Experimental Results. 4.6. Summary. 5: Multiple Scan Chains. 5.1. Introduction. 5.2. Multiple Scan Chain-Based DFT Architecture. 5.3. Multiple Scan Chains Generation. 5.4. Experimental Results. 5.5. Summary. 6: Power-Conscious Test Synthesis and Scheduling. 6.1. Introduction. 6.2. Power Dissipation in BIST Data Paths. 6.3. Effect of Test Synthesis and Scheduling. 6.4. Power-Conscious Test Synthesis and Scheduling Algorithm. 6.5. Experimental Results. 6.6. Summary. 7: Power Profile Manipulation. 7.1. Introduction. 7.2. The Global Peak Power Approximation Model. 7.3. Power Profile Manipulation. 7.4. Power-Constrained Test Scheduling. 7.5. Experimental Results. 7.6. Summary. 8: Conclusion.