Practical Low Power Digital VLSI Design

Practical Low Power Digital VLSI Design emphasizes the optimization and trade-off techniques that involve power dissipation, in the hope that the readers are better prepared the next time they are presented with a low power design problem. The book highlights the basic principles, methodologies and techniques that are common to most CMOS digital designs. The advantages and disadvantages of a particular low power technique are discussed. Besides the classical area-performance trade-off, the impact to design cycle time, complexity, risk, testability and reusability are discussed. The wide impacts to all aspects of design are what make low power problems challenging and interesting. Heavy emphasis is given to top-down structured design style, with occasional coverage in the semicustom design methodology. The examples and design techniques cited have been known to be applied to production scale designs or laboratory settings. The goal of Practical Low Power Digital VLSI Design is to permit the readers to practice the low power techniques using current generation design style and process technology.
Practical Low Power Digital VLSI Design considers a wide range of design abstraction levels spanning circuit, logic, architecture and system. Substantial basic knowledge is provided for qualitative and quantitative analysis at the different design abstraction levels. Low power techniques are presented at the circuit, logic, architecture and system levels. Special techniques that are specific to some key areas of digital chip design are discussed as well as some of the low power techniques that are just appearing on the horizon.
Practical Low Power Digital VLSI Design will be of benefit to VLSI design engineers and students who have a fundamental knowledge of CMOS digital design.

1 Introduction.- 1.1 Needs for Low Power VLSI Chips.- 1.2 Charging and Discharging Capacitance.- 1.3 Short-circuit Current in CMOS Circuit.- 1.3.1 Short-circuit Current of an Inverter.- 1.3.2 Short-circuit Current Variation with Output Load.- 1.3.3 Short-circuit Current Variation with Input Signal Slope.- 1.4 CMOS Leakage Current.- 1.4.1 Reverse Biased PN-junction.- 1.4.2 Subthreshold Channel Leakage.- 1.4.3 Leakage Current in Digital Design.- 1.5 Static Current.- 1.6 Basic Principles of Low Power Design.- 1.6.1 Reduce Switching Voltage.- 1.6.2 Reduce Capacitance.- 1.6.3 Reduce Switching Frequency.- 1.6.4 Reduce Leakage and Static Current.- 1.7 Low Power Figure of Merits.- 2 Simulation Power Analysis.- 2.1 SPICE Circuit Simulation.- 2.1.1 SPICE Basics.- 2.1.2 SPICE Power Analysis.- 2.2 Discrete Transistor Modeling and Analysis.- 2.2.1 Tabular Transistor Model.- 2.2.2 Switch Level Analysis.- 2.3 Gate-level Logic Simulation.- 2.3.1 Basics of Gate-level Analysis.- 2.3.2 Capacitive Power Dissipation.- 2.3.3 Internal Switching Energy.- 2.3.4 Static State Power.- 2.3.5 Gate-level Capacitance Estimation.- 2.3.6 Gate-level Power Analysis.- 2.4 Architecture-level Analysis.- 2.4.1 Power Models Based on Activities.- 2.4.2 Power Model Based on Component Operations.- 2.4.3 Abstract Statistical Power Models.- 2.5 Data Correlation Analysis in DSP Systems.- 2.5.1 Dual Bit Type Signal Model.- 2.5.2 Datapath Module Characterization and Power Analysis.- 2.6 Monte Carlo Simulation.- 2.6.1 Statistical Estimation of Mean.- 2.6.2 Monte Carlo Power Simulation.- 3 Probabilistic Power Analysis.- 3.1 Random Logic Signals.- 3.1.1 Characterization of Logic Signals.- 3.1.2 Continuous and Discrete Random Signals.- 3.2 Probability and Frequency.- 3.2.1 Static Probability and Frequency.- 3.2.2 Conditional Probability and Frequency.- 3.2.3 Word-level and Bit-level Statistics.- 3.3 Probabilistic Power Analysis Techniques.- 3.3.1 Propagation of Static Probability in Logic Circuits.- 3.3.2 Transition Density Signal Model.- 3.3.3 Propagation of Transition Density.- 3.3.4 Gate Level Power Analysis Using Transition Density.- 3.4 Signal Entropy.- 3.4.1 Basics of Entropy.- 3.4.2 Power Estimation Using Entropy.- 4 Circuit.- 4.1 Transistor and Gate Sizing.- 4.1.1 Sizing an Inverter Chain.- 4.1.2 Transistor and Gate Sizing for Dynamic Power Reduction.- 4.1.3 Transistor Sizing for Leakage Power Reduction.- 4.2 Equivalent Pin Ordering.- 4.3 Network Restructuring and Reorganization.- 4.3.1 Transistor Network Restructuring.- 4.3.2 Transistor Network Partitioning and Reorganization.- 4.4 Special Latches and Flip-flops.- 4.4.1 Flip-Flop and Latch Circuits.- 4.4.2 Self-gating Flip-flop.- 4.4.3 Combinational Flip-flop.- 4.4.4 Double Edge Triggered Flip-flop.- 4.5 Low Power Digital Cell Library.- 4.5.1 Cell Sizes and Spacing.- 4.5.2 Varieties of Boolean Functions.- 4.6 Adjustable Device Threshold Voltage.- 5 Logic.- 5.1 Gate Reorganization.- 5.1.1 Local Restructuring.- 5.2 Signal Gating.- 5.3 Logic Encoding.- 5.3.1 Binary versus Gray Code Counting.- 5.3.2 Bus Invert Encoding.- 5.4 State Machine Encoding.- 5.4.1 Transition Analysis of State Encoding.- 5.4.2 Output Don’t-care Encoding.- 5.4.3 Design Trade-offs in State Machine Encoding.- 5.5 Precomputation Logic.- 5.5.1 Basics of Precomputation Logic.- 5.5.2 Precomputation Condition.- 5.5.3 Alternate Precomputation Architectures.- 5.5.4 Design Issues in Precomputation Logic Technique.- 6 Special Techniques.- 6.1 Power Reduction in Clock Networks.- 6.1.1 Clock Gating.- 6.1.2 Reduced Swing Clock.- 6.1.3 Oscillator Circuit for Clock Generation.- 6.1.4 Frequency Division and Multiplication.- 6.1.5 Other Clock Power Reduction Techniques.- 6.2 CMOS Floating Node.- 6.2.1 Tristate Keeper Circuit.- 6.2.2 Blocking Gate.- 6.3 Low Power Bus.- 6.3.1 Low Swing Bus.- 6.3.2 Charge Recycling Bus.- 6.4 Delay Balancing.- 6.5 Low Power Techniques for SRAM.- 6.5.1 SRAM Cell.- 6.5.2 Memory Bank Partitioning.- 6.5.3 Pulsed Wordline and Reduced Bitline Swing.- 6.5.4 Case Study: Design of an FIFO Buffer.- 7 Architecture and System.- 7.1 Power and Performance Management.- 7.1.1 Microprocessor Sleep Modes.- 7.1.2 Performance Management.- 7.1.3 Adaptive Filtering.- 7.2 Switching Activity Reduction.- 7.2.1 Guarded Evaluation.- 7.2.2 Bus Multiplexing.- 7.2.3 Glitch Reduction by Pipelining.- 7.3 Parallel Architecture with Voltage Reduction.- 7.4 Flow Graph Transformation.- 7.4.1 Operator Reduction.- 7.4.2 Loop Unrolling.- 8 Advanced Techniques.- 8.1 Adiabatic Computation.- 8.1.1 Complementary Adiabatic Logic.- 8.1.2 Power Efficiency of Adiabatic Logic.- 8.2 Pass Transistor Logic Synthesis.- 8.2.1 Basics of Pass Transistor Logic.- 8.2.2 Boolean Decision Diagram and Pass Transistor Logic.- 8.2.3 Pass Transistor Logic Synthesis System.- 8.3 Asynchronous Circuits.- 8.3.1 Asynchronous System Basics.- 8.3.2 Prospects of Asynchronous Computation.