Principles of Verifiable RTL Design: A functional coding style supporting verification processes in Verilog.

Bening, Lionel and Harry D. Foster:

ISBN 10: 0792373685 / ISBN 13: 9780792373681

Editore: Springer, 2001

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282 Seiten; Das hier angebotene Buch stammt aus einer teilaufgelösten wissenschaftlichen Bibliothek und trägt die entsprechenden Kennzeichnungen (Rückenschild, Instituts-Stempel.); Schnitt und Einband sind etwas staubschmutzig; der Buchzustand ist ansonsten ordentlich und dem Alter entsprechend gut. Text in ENGLISCHER Sprache! Sprache: Englisch Gewicht in Gramm: 660.

Codice articolo 1593713

Dati bibliografici

• Titolo: Principles of Verifiable RTL Design: A functional coding style supporting verification processes in Verilog.
• Editore: Springer
• Data di pubblicazione: 2001
• Lingua: Inglese
• ISBN 10: 0792373685
• ISBN 13: 9780792373681
• Rilegatura: gebundene Ausgabe
• Edizione: 2nd edition;.
• Condizione: Gut
• Peso: 660 grammi
• Cataloghi dei venditori:
  • 202 Informatik & EDV

Descrizione articolo

Riassunto

System designers, computer scientists and engineers have c- tinuously invented and employed notations for modeling, speci- ing, simulating, documenting, communicating, teaching, verifying and controlling the designs of digital systems. Initially these s- tems were represented via electronic and fabrication details. F- lowing C. E. Shannon’s revelation of 1948, logic diagrams and Boolean equations were used to represent digital systems in a fa- ion that de-emphasized electronic and fabrication detail while revealing logical behavior. A small number of circuits were made available to remove the abstraction of these representations when it was desirable to do so. As system complexity grew, block diagrams, timing charts, sequence charts, and other graphic and symbolic notations were found to be useful in summarizing the gross features of a system and describing how it operated. In addition, it always seemed necessary or appropriate to augment these documents with lengthy verbal descriptions in a natural language. While each notation was, and still is, a perfectly valid means of expressing a design, lack of standardization, conciseness, and f- mal definitions interfered with communication and the understa- ing between groups of people using different notations. This problem was recognized early and formal languages began to evolve in the 1950s when I. S. Reed discovered that flip-flop input equations were equivalent to a register transfer equation, and that xvi tor-like notation. Expanding these concepts Reed developed a no- tion that became known as a Register Transfer Language (RTL).

Contenuti

Foreword. Preface. 1. Introduction. 2. The Verification Process. 3. Coverage, Events and Assertions. 4. RTL Methodology Basics. 5. RTL Logic Simulation. 6. RTL Formal Verification. 7. Verifiable RTL Style. 8. The Bad Stuff. 9. Verifiable RTL Tutorial. 10. Principles of Verifiable RTL Design. Bibliography. A. Comparing Verilog Construct Performance. B. Quick Reference. C. Assertion Monitors.