Pyramidal Systems for Computer Vision

Stefano Levialdi

ISBN 10: 3642829422 / ISBN 13: 9783642829420

Editore: Springer Berlin Heidelberg, 2011

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Druck auf Anfrage Neuware - Printed after ordering - This book contains the proceedings of the NATO Advanced Research Workshop held in Maratea (Italy), May 5-9, 1986 on Pyramidal Systems for Image Processing and Computer Vision. We had 40 participants from 11 countries playing an active part in the workshop and all the leaders of groups that have produced a prototype pyramid machine or a design for such a machine were present. Within the wide field of parallel architectures for image processing a new area was recently born and is growing healthily: the area of pyramidally structured multiprocessing systems. Essentially, the processors are arranged in planes (from a base to an apex) each one of which is generally a reduced (usually by a power of two) version of the plane underneath: these processors are horizontally interconnected (within a plane) and vertically connected with 'fathers' (on top planes) and 'children' on the plane below. This arrangement has a number of interesting features, all of which were amply discussed in our Workshop including the cellular array and hypercube versions of pyramids. A number of projects (in different parts of the world) are reported as well as some interesting applications in computer vision, tactile systems and numerical calculations.

Codice articolo 9783642829420

Dati bibliografici

• Titolo: Pyramidal Systems for Computer Vision
• Editore: Springer Berlin Heidelberg
• Data di pubblicazione: 2011
• Lingua: Inglese
• ISBN 10: 3642829422
• ISBN 13: 9783642829420
• Rilegatura: Taschenbuch
• Condizione: Neu
• Dimensioni: 244 L x 170 A x 23 P (millimetri) 244 millimetri di larghezza per 170 millimetri di altezza per 23 millimetri di profondità
• Peso: 701 grammi

Descrizione articolo

Riassunto

This book contains the proceedings of the NATO Advanced Research Workshop held in Maratea (Italy), May 5-9, 1986 on Pyramidal Systems for Image Processing and Computer Vision. We had 40 participants from 11 countries playing an active part in the workshop and all the leaders of groups that have produced a prototype pyramid machine or a design for such a machine were present. Within the wide field of parallel architectures for image processing a new area was recently born and is growing healthily: the area of pyramidally structured multiprocessing systems. Essentially, the processors are arranged in planes (from a base to an apex) each one of which is generally a reduced (usually by a power of two) version of the plane underneath: these processors are horizontally interconnected (within a plane) and vertically connected with "fathers" (on top planes) and "children" on the plane below. This arrangement has a number of interesting features, all of which were amply discussed in our Workshop including the cellular array and hypercube versions of pyramids. A number of projects (in different parts of the world) are reported as well as some interesting applications in computer vision, tactile systems and numerical calculations.

Contenuti

Parallel, Hierarchical Software/Hardware Pyramid Architectures.- I.P. Hierarchical Systems: Architectural Features.- General Purpose Pyramidal Architectures.- Pyramids ― Expected Performance.- Hypercubes and Pyramids.- Architectural Comparisons.- A Pyramidal System for Image Processing.- Counting on the GAM Pyramid.- A Pipelined Pyramid Machine.- The PAPIA Controller: Hardware Implementation.- Custom Made Pyramids.- Paradigms for Pyramid Machine Algorithms.- Pyramid Algorithms on Processor Arrays.- Pyramidal Transforms in Image Processing and Computer Vision.- Overlapping in Compact Pyramids.- Some Pyramid Techniques for Image Segmentation.- Segmentation of Textured Images by Pyramid Linking.- Local Motion Estimation with the Dynamic Pyramid.- Vectorial Features in Pyramidal Image Processing.- Programming Image Processing Machines.- A High Level Language for Pyramidal Architectures.- Tactile Information Processing.- Silicon Implementation of Multiprocessor Pyramid Architecture.- Fault-Tolerance Techniques in Arrays for Image Processing.