Quick-Turnaround ASIC Design in VHDL: Core-Based Behavioral Synthesis (The Springer International Series in Engineering and Computer Science (367))

Bouden-Romdhane, N., Madisetti, Vijay, Hines, J.W.

ISBN 10: 1461286123 / ISBN 13: 9781461286127

Editore: Springer, 2011

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Dati bibliografici

• Titolo: Quick-Turnaround ASIC Design in VHDL: Core-Based Behavioral Synthesis (The Springer International Series in Engineering and Computer Science (367))
• Editore: Springer
• Data di pubblicazione: 2011
• Lingua: Inglese
• ISBN 10: 1461286123
• ISBN 13: 9781461286127
• Rilegatura: Paperback
• Condizione: Like New
• Tipo di libro: book

Descrizione articolo

Riassunto

From the Foreword.....
Modern digital signal processing applications provide a large challenge to the system designer. Algorithms are becoming increasingly complex, and yet they must be realized with tight performance constraints. Nevertheless, these DSP algorithms are often built from many constituent canonical subtasks (e.g., IIR and FIR filters, FFTs) that can be reused in other subtasks. Design is then a problem of composing these core entities into a cohesive whole to provide both the intended functionality and the required performance.
In order to organize the design process, there have been two major approaches. The top-down approach starts with an abstract, concise, functional description which can be quickly generated. On the other hand, the bottom-up approach starts from a detailed low-level design where performance can be directly assessed, but where the requisite design and interface detail take a long time to generate. In this book, the authors show a way to effectively resolve this tension by retaining the high-level conciseness of VHDL while parameterizing it to get good fit to specific applications through reuse of core library components. Since they build on a pre-designed set of core elements, accurate area, speed and power estimates can be percolated to high- level design routines which explore the design space. Results are impressive, and the cost model provided will prove to be very useful. Overall, the authors have provided an up-to-date approach, doing a good job at getting performance out of high-level design.
The methodology provided makes good use of extant design tools, and is realistic in terms of the industrial design process. The approach is interesting in its own right, but is also of direct utility, and it will give the existing DSP CAD tools a highly competitive alternative. The techniques described have been developed within ARPAs RASSP (Rapid Prototyping of Application Specific SignalProcessors) project, and should be of great interest there, as well as to many industrial designers.
Professor Jonathan Allen, Massachusetts Institute of Technology

Contenuti

1 Introduction.- 1.1 Problem Description.- 1.2 Design Maturity Layers.- 1.3 Proposed Approach.- 1.4 Market Trends.- 1.5 Organization of the Monograph.- 2 Background.- 2.1 The Role of ASICs.- 2.2 ASIC and ASSP design approaches.- 2.3 Classification of approaches.- 2.4 Model for Design Costs.- 2.5 Conclusion.- 3 VHDL-Based Design.- 3.1 VHDL Motivation.- 3.2 Parameterized Design with VHDL.- 3.3 Systematic DwR.- 4 Design for Reuse.- 4.1 Introduction.- 4.2 Core Design View.- 4.3 System Design View.- 4.4 Simulation Design View.- 4.5 Cost Model.- 5 Design with Reuse.- 5.1 Filter Synthesis.- 5.2 FFT Synthesis.- 6 Board Integration.- 6.1 Introduction.- 6.2 Current Design Practice.- 6.3 Virtual Prototyping.- 6.4 Board-Level Modeling.- 6.5 A Case Study.- 6.6 Conclusion.- 7 Conclusions.- 7.1 Highlights.- 7.2 Future Work.- A DwR Software.- A.1 An ADL-FIR Design.- References.