Reuse Methodology Manual for System-on-a-Chip Designs (Third Edition)

Keating, Michael; Bricaud, Pierre

ISBN 10: 1402071418 / ISBN 13: 9781402071416

Editore: Kluwer Academic Publishers, Boston, 2002

Riguardo questo articolo

Hardcover, [xviii], 291 pages. Near Fine condition. Third edition. Size 9.5"x6.25". "Silicon and tool technologies move so quickly that many of the details of design-for-reuse will undoubtedly continue to evolve over time. But the fundamental aspects of the methodology described in this book have become widely adopted and are likely to form the foundation of chip design for some time to come. . . . Features of the Third Edition: Up to date; State of the art; Reuse as a solution for circuit designers; A chronicle of 'best practices'; All chapters updated and revised; Generic guidelines - non tool specific; Emphasis on hard IP and physical design." Book has light exterior shelfwear. Previous owner's name blacked-out on top edge, text else Fine condition, clean and unmarked.

Codice articolo 009472

Dati bibliografici

• Titolo: Reuse Methodology Manual for System-on-a-Chip Designs (Third Edition)
• Editore: Kluwer Academic Publishers, Boston
• Data di pubblicazione: 2002
• Lingua: Inglese
• ISBN 10: 1402071418
• ISBN 13: 9781402071416
• Rilegatura: Rilegato
• Edizione: terza edizione
• Condizione: Near Fine
• Cataloghi dei venditori:
  • Internet Listing

Descrizione articolo

Riassunto

The authors (both of Synopsys, Inc.) present the results of a collaborative project between their company and Mentor Graphics to develop, demonstrate, and document an intellectual property reuse-based design methodology for large numbered gate computer chips. They discuss system-level design issues, the design process, coding guidelines, synthesis and verification, deployment, system integration, and data and project management. Annotation (c) Book News, Inc., Portland, OR (booknews.com)

Dalla quarta di copertina

Features of the Third Edition:

• UP TO DATE
• STATE OF THE ART
• REUSE AS A SOLUTION FOR CIRCUIT DESIGNERS
• A CHRONICLE OF "BEST PRACTICES"
• ALL CHAPTERS UPDATED AND REVISED
• GENERIC GUIDELINES-NON TOOL SPECIFIC
• EMPHASIS ON HARD IP AND PHYSICAL DESIGN

Reuse Methodology Manual for System-on-a-Chip Designs, Third Edition outlines a set of best practices for creating reusable designs for use in a SoC design methodology. These practices are based on the authors' experience in developing reusable designs, as well as the experience of design teams in many companies around the world. Silicon and tool technologies move so quickly that many of the details of design-for-reuse will undoubtedly continue to evolve over time. But the fundamental aspects of the methodology described in this book have become widely adopted and are likely to form the foundation of chip design for some time to come.

Development methodology necessarily differs between system designers and processor designers, as well as between DSP developers and chipset developers. However, there is a common set of problems facing everyone who is designing complex chips.

In response to these problems, design teams have adopted a block-based design approach that emphasizes design reuse. Reusing macros (sometimes called "cores") that have already been designed and verified helps to address all of the problems above. However, in adopting reuse-based design, design teams have run into a significant problem. Reusing blocks that have not been explicitly designed for reuse has often provided little or no benefit to the team. The effort to integrate a pre-existing block into new designs can become prohibitively high, if the block does not provide the right views, the right documentation, and the right functionality.

From this experience, design teams have realized that reuse-based design requires an explicit methodology for developing reusable macros that are easy to integrate into SoC designs. This manual focuses on describing these techniques.