Source-Synchronous Networks-On-Chip : Circuit and Architectural Interconnect Modeling

Ayan Mandal, Rabi Mahapatra, Sunil P. Khatri

ISBN 10: 1461494044 / ISBN 13: 9781461494041

Editore: Springer New York, 2013

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Zustand: Hervorragend | Sprache: Englisch | Produktart: Bücher | This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

Codice articolo 24295134/1

Dati bibliografici

• Titolo: Source-Synchronous Networks-On-Chip : Circuit and Architectural Interconnect Modeling
• Editore: Springer New York
• Data di pubblicazione: 2013
• Lingua: Inglese
• ISBN 10: 1461494044
• ISBN 13: 9781461494041
• Rilegatura: Rilegato
• Condizione: Hervorragend
• Cataloghi dei venditori:
  • Bücher

Descrizione articolo

Riassunto

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

Dalla quarta di copertina

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

• Describes novel methods for high-speed network-on-chip (NoC) design;
• Enables readers to understand NoC design from both circuit and architectural levels;
• Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC;
• Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.