System-Level Calibration for Memories under Process Variability Impact : An Assessment by Developing a VHDL Controller/Demonstrator

Florian Lobmaier

ISBN 10: 363903886X / ISBN 13: 9783639038866

Editore: VDM Verlag Dr. Müller, 2008

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nach der Bestellung gedruckt Neuware - Printed after ordering - In microelectronics technology scaling is performed in orderto improve the performance and cost of embedded systems. Scaling to the minimum feature sizes below 100 nm, however, causes a host of problems. One of the most important problems is process variability which is a variation of device parameters after fabrication. Since process variability increases by downscaling the silicon integration technology minimum geometry transistors are heavily affected. Therefore the focus of this book are small on-chip memories in the lowest layer of a memory hierarchy. Process variability severely impacts the performance and the energy consumption of memory organizations. RTL simulations suggest that process variability slows down the memories and makes them consume more energy in most cases. This degrades the parametric- orsystem-yield after fabrication. To improve on the current standard corner-point design techniques, which produce huge overheads in energy and delay, IMEC introduces configurable memories. This book introduces a controller which is able to put such memories in a state were all requirements are met by minimum energy consumption.

Codice articolo 9783639038866

Dati bibliografici

• Titolo: System-Level Calibration for Memories under Process Variability Impact : An Assessment by Developing a VHDL Controller/Demonstrator
• Editore: VDM Verlag Dr. Müller
• Data di pubblicazione: 2008
• Lingua: Inglese
• ISBN 10: 363903886X
• ISBN 13: 9783639038866
• Rilegatura: Taschenbuch
• Condizione: Neu
• Dimensioni: 220 L x 150 A x 5 P (millimetri) 220 millimetri di larghezza per 150 millimetri di altezza per 5 millimetri di profondità
• Peso: 132 grammi

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Riassunto

In microelectronics technology scaling is performed in order to im­prove the performance and cost of embedded systems. Scaling to the minimum feature sizes below 100 nm, however, causes a host of problems. One of the most important problems is process variability which is a variation of device parameters after fabrication. Since process variability increases by downscaling the silicon integration technology minimum geometry transistors are heavily affected. Therefore the focus of this book are small on-chip memories in the lowest layer of a memory hierarchy. Process variability severely im­pacts the performance and the energy consumption of memory organizations. RTL simulations suggest that process variability slows down the memories and makes them consume more energy in most cases. This degrades the parametric- or system-yield after fabrication. To improve on the current standard corner-point design techniques, which produce huge overheads in energy and delay, IMEC introduces configurable memories. This book introduces a controller which is able to put such memories in a state were all requirements are met by minimum energy con­sumption.