Timing Analysis and Simulation for Signal Integrity Engineers

Edlund, Greg

ISBN 10: 0132365049 / ISBN 13: 9780132365048

Editore: Prentice Hall PTR, 2007

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Riassunto:

Every day, companies call upon their signal integrity engineers to make difficult decisions about design constraints and timing margins.Can I move these wires closer together? How many holes can I drill in this net? How far apart can I place these chips? Each design is unique: theres no single recipe that answers all the questions. Todays designs require ever greater precision, but design guides for specific digital interfaces are by nature conservative. Now, for the first time, theres a complete guide to timing analysis and simulation that will help you manage the tradeoffs between signal integrity, performance, and cost.

Writing from the perspective of a practicing SI engineer and team lead, Greg Edlund of IBM presents deep knowledge and quantitative techniques for making better decisions about digital interface design. Edlund shares his insights into how and why digital interfaces fail, revealing how fundamental sources of pathological effects can combine to create fault conditions. You wont just learn Edlunds expert techniques for avoiding failures: youll learn how to develop the right approach foryour own projects and environment.

Coverage includes

Systematically ensure that interfaces will operate with positive timing margin over the products lifetimewithout incurring excess cost

Understand essential chip-to-chip timing concepts in the context of signal integrity

Collect the right information upfront, so you can analyze new designs more effectively

Review the circuits that store information in CMOS state machinesand how they fail

Learn how to time common-clock, source synchronous, and high-speed serial transfers

Thoroughly understand how interconnect electrical characteristics affect timing: propagation delay, impedance profile, crosstalk, resonances, and frequency-dependent loss

Model 3D discontinuities using electromagnetic field solvers

Walk through four case studies: coupled differential vias, land grid array connector, DDR2 memory data transfer, and PCI Express channel

Appendices present a refresher on SPICE modeling and a high-level conceptual framework for electromagnetic field behavior

Objective, realistic, and practical, this is the signal integrity resource engineers have been searching for.

Preface xiii

Acknowledgments xvi

About the Author xix

About the Cover xx

Chapter 1: Engineering Reliable Digital Interfaces 1

Chapter 2: Chip-to-Chip Timing 13

Chapter 3: Inside IO Circuits 39

Chapter 4: Modeling 3D Discontinuities 73

Chapter 5: Practical 3D Examples 101

Chapter 6: DDR2 Case Study 133

Chapter 7: PCI Express Case Study 175

Appendix A: A Short CMOS and SPICE Primer 209

Appendix B: A Stroll Through 3D Fields 219

Endnotes 233

Index 235

Informazioni sull?autore:

Greg Edlunds career in signal integrity began in 1988 at Supercomputer Systems, Inc., where he simulated and measured timing characteristics of bipolar embedded RAMs used in the computers vector registers. Since then, he has participated in the development and testing of nine other high-performance computing platforms for Cray Research, Inc., Digital Equipment Corp., and IBM Corp. He has had the good fortune of learning from many talented engineers while focusing his attention on modeling, simulation, and measurement of IO circuits and interconnect components. A solid physical foundation and practical engineering experience combine to form a valuable perspective on optimizing performance, reliability, and cost.

Dati bibliografici

Titolo: Timing Analysis and Simulation for Signal ...
Casa editrice: Prentice Hall PTR
Data di pubblicazione: 2007
Legatura: Hardcover
Condizione: Good