Tunnel Field-effect Transistors (TFET): Modelling and Simulation Format: Hardcover

Research into Tunneling Field Effect Transistors (TFETs) has developed significantly in recent times, indicating their significance in low power integrated circuits. This book describes the qualitative and quantitative fundamental concepts of TFET functioning, the essential components of the problem of modelling the TFET, and outlines the most commonly used mathematical approaches for the same in a lucid language.

Divided into eight chapters, the topics covered include: Quantum Mechanics, Basics of Tunneling, The Tunnel FET, Drain current modelling of Tunnel FET: The task and its challenges, Modeling the Surface Potential in TFETs, Modelling the Drain Current, and Device simulation using Technology Computer Aided Design (TCAD). The information is well organized, describing different phenomena in the TFETs using simple and logical explanations.

Key features:

* Enables readers to understand the basic concepts of TFET functioning and modelling in order to read, understand, and critically analyse current research on the topic with ease.

* Includes state-of-the-art work on TFETs, attempting to cover all the recent research articles published on the subject.

* Discusses the basic physics behind tunneling, as well as the device physics of the TFETs.

* Provides detailed discussion on device simulations along with device physics so as to enable researchers to carry forward their study on TFETs.

Primarily targeted at new and practicing researchers and post graduate students, the book would particularly be useful for researchers who are working in the area of compact and analytical modelling of semiconductor devices.

Dr. M. Jagadesh Kumar obtained his MS in Electrical Engineering (EE) and PhD in EE from the Indian Institute of Technology (IIT), Madras. He is currently the NXP (Philips) Chair Professor at IIT Delhi by Philips Semiconductors, Netherlands (now NXP Semiconductors India Pvt Ltd). He works in the area of Nanoelectronic Devices, Nanoscale Device modeling and simulation, Innovative Device Design and Power semiconductor devices. He has published extensively in the above areas with four book chapters and more than 200 publications in refereed journals and conference proceedings including 70 IEEE Journal papers. Six patent applications have been filed based on his research.

Rajat Vishnoi received his B.Tech degree in EE from the Indian Institute of Technology (IIT), Kanpur, in 2012. He is currently pursuing his Ph.D. degree in Electrical Engineering at the Indian Institute of Technology, Delhi. His research interests include semiconductor device modelling, design and fabrication.

Pratyush Pandey completed his undergraduate in Electrical Engineering from the Indian Institute of Technology (IIT), Kanpur, in 2011. In 2007 he received a Silver Medal in the International Physics Olympiad, and a Gold Medal in the Indian National Chemistry Olympiad. During his undergraduate studies, he worked on quantum error correction codes, quantum cryptography, and applied information theory. Subsequently, he worked as a Research Assistant at IIT Delhi on the analytical modelling of TFETs. He has developed analytical models for Double Gate, Dual Material Gate, and Nanowire TFETs. He is currently a graduate student advised by Dr. Alan Seabaugh at Notre Dame, where he is involved in the simulation, modelling, characterisation, and fabrication of TMD TFETs. He is also a reviewer for IEEE Transactions on Electron Devices, and the Journal of Computational Electronics.