The VHDL Handbook

This book is intended to be a working reference for electronic hardware de­ signers who are interested in writing VHDL models. A handbook/cookbook approach is taken, with many complete examples used to illustrate the fea­ tures of the VHDL language and to provide insight into how particular classes of hardware devices can be modelled in VHDL. It is possible to use these models directly or to adapt them to similar problems with minimal effort. This book is not intended to be a complete reference manual for the VHDL language. It is possible to begin writing VHDL models with little background in VHDL by copying examples from the book and adapting them to particular problems. Some exposure to the VHDL language prior to using this book is recommended. The reader is assumed to have a solid hardware design background, preferably with some simulation experience. For the reader who is interested in getting a complete overview of the VHDL language, the following publications are recommended reading: • An Introduction to VHDL: Hardware Description and Design [LIP89] • IEEE Standard VHDL Language Reference Manual [IEEE87] • Chip-Level Behavioral Modelling [ARMS88] • Multi-Level Simulation of VLSI Systems [COEL87] Other references of interest are [USG88], [DOD88] and [CLSI87] Use of the Book If the reader is familiar with VHDL, the models described in chapters 3 through 7 can be applied directly to design problems.

1 Introduction.- 1.1 Introduction to the VHDL Language.- 1.1.1 History of VHDL.- 1.1.2 DOD Requirements and VHDL.- 1.1.3 VHDL As a Design Tool.- 1.2 Multi-Level Design.- 1.3 The Model Accuracy Continuum.- 2 Anatomy of a VHDL Model.- 2.1 Describing Electronic Hardware in VHDL.- 2.2 A VHDL File.- 2.3 The Standard Logic Package.- 2.4 User Defined Packages.- 2.5 VHDL Models and the Accuracy Continuum.- 2.5.1 2-Value Unit-Delay Approach.- 2.5.2 46-Value Unit-Delay Approach.- 2.5.3 Fixed-Delay Approach.- 2.5.4 Variable-Delay Approach.- 2.5.5 Generic Variable-Delay Approach.- 2.5.6 Full-Delay Approach.- 2.5.7 Error Checking and Model Structure.- 2.6 Handling Timing Using Configurations.- 2.7 Using VHDL as a Stimulus Language.- 2.8 Standardized VHDL Modelling Conventions.- 2.8.1 Generic Parameters.- 2.8.2 Naming Conventions.- 2.8.3 Constraints.- 2.8.4 Unknown Handling.- 3 Combinational Devices.- 3.1 Simple Gates.- 3.1.1 2-Input Positive-Nand Gate.- 3.1.2 2-Input Positive-Nand with Open-Collector Outputs.- 3.1.3 2-Input Positive-Nor Gate.- 3.1.4 Inverter.- 3.1.5 Inverter with Open-Collector Outputs.- 3.1.6 3-Input Positive-And Gate.- 3.1.7 3-Input Positive-Nand Gate.- 3.1.8 2-Input Positive-Or Gate.- 3.1.9 2-Input Positive-Xor Gate.- 3.2 Selectors/Multiplexers.- 3.2.1 3 to 8 Decoder/Multiplexer.- 3.2.2 2 to 4 Decoder/Multiplexer.- 3.2.3 1 of 8 Selector/Multiplexer.- 3.2.4 1 of 4 Selector/Multiplexer.- 3.2.5 1 of 2 Selector/Multiplexer.- 3.3 Switch Level Devices.- 3.3.1 Switch Modelling Utilities.- 3.3.2 Bidirectional Transmission Element.- 3.3.3 Basic Complementary Transmission Gate.- 3.3.4 Basic Transmission Gate.- 3.4 Simple ALU’s.- 3.4.1 ALU/Function Generator.- 3.5 One Shots.- 3.5.1 Monostable Multivibrator.- 3.6 Comparators.- 3.6.1 4 Bit Magnitude Comparator.- 3.7 Parity Generators/Checkers.- 3.7.1 9 bit Odd/Even Parity Generator/Checker.- 4 Sequential Devices.- 4.1 Flip-Flops.- 4.1.1 D-Type Positive-Edge Triggered Flip-Flop with Preset/Clear.- 4.1.2 JK Pos-Edge Triggered Flip-Flop with Preset/Clear.- 4.1.3 JK Neg-Edge Triggered Flip-Flop with Preset/Clear.- 4.1.4 JK Negative-Edge Triggered Flip-Flop with Preset.- 4.2 Registers.- 4.2.1 4-Bit Parallel-Access Shift Register.- 4.2.2 3 to 8 Decoder/Demultiplexer with Register.- 4.2.3 3 to 8 Decoder/Demultiplexer with Latch.- 4.2.4 8 Bit Parallel-Out Serial Shift Register.- 4.2.5 Parallel Load 8 Bit Shift Register.- 4.2.6 Parallel Load 8 Bit Shift Register with Clear.- 4.3 Counters.- 4.3.1 Synchronous 4 Bit Decade Counter with Asynchronous Clear.- 4.3.2 Synchronous 4 Bit Binary Counter with Asynchronous Clear.- 4.3.3 Synchronous 4 Bit Decade Counter.- 4.3.4 Synchronous 4 Bit Binary Counter.- 4.3.5 Synchronous Up/Down 4-Bit Decade Counter.- 5 Memory Devices.- 5.1 Memory Initialization.- 5.2 Read Only Memories.- 5.2.1 1024 bit (256 by 4) ROM.- 5.2.2 16,384 bit (4096 by 4) register PROM.- 5.3 Random Access Memories.- 5.3.1 64 bit RAM.- 5.4 PALs, PLDs.- 5.4.1 Calculating Products.- 5.4.2 10 input, 2 output, 6 I/O PAL.- 5.4.3 8 input, 2 I/O, 6 clocked output PAL.- 5.4.4 8 input, 8 clocked output PAL.- 6 Complex Devices.- 6.1 Getting Started.- 6.1.1 Partial versus Full Functional Models.- 6.1.2 Architecture.- 6.1.3 Behavior.- 6.2 The Timing Model.- 6.2.1 Device Speeds.- 6.2.2 Min/Max Timing.- 6.2.3 Drive/Loading Dependencies.- 6.2.4 A Uniform Approach to Device Dependent Data.- 6.3 Error Handling.- 6.3.1 Unknowns.- 6.3.2 Setup/Hold Time Techniques.- 6.3.3 Waveform Checking.- 6.4 Techniques for Modeling.- 6.4.1 Bus Handlers.- 6.4.2 Instruction Decoders.- 6.4.3 Sequencers.- 6.4.4 Instruction Sets.- 6.5 Quality Assurance.- 6.5.1 Developing a Test Plan.- 6.5.2 Validation of the Model.- 7 The Standard Logic Package.- 7.1 Using the Standard Logic Package.- 7.2 The Logic Value System.- 7.3 Technology Rules.- 7.3.1 ECL ― Emitter Coupled Logic.- 7.3.2 CMOS ― Complementary MOS.- 7.3.3 NMOS ― n-Channel MOS.- 7.3.4 TTL ― Transistor transistor logic.- 7.3.5 TTLOC ― Open-collector TTL.- 7.4 Bus Resolution.- 7.5 Logic Manipulation.- 7.5.1 Overloaded Comparison Operators.- 7.5.2 State/Strength Lookup Tables.- 7.5.3 Logic Lookup Tables.- 7.6 Timing Utilities.- 7.7 Integer Data Utilities.