VHDL for Simulation, Synthesis and Formal Proofs of Hardware (The Springer International Series in Engineering and Computer Science, 183)

Mermet, Jean

ISBN 10: 0792392531 / ISBN 13: 9780792392538

Editore: Springer (edition 1992), 1992

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Codice articolo 0792392531-7-1

Dati bibliografici

• Titolo: VHDL for Simulation, Synthesis and Formal Proofs of Hardware (The Springer International Series in Engineering and Computer Science, 183)
• Editore: Springer (edition 1992)
• Data di pubblicazione: 1992
• Lingua: Inglese
• ISBN 10: 0792392531
• ISBN 13: 9780792392538
• Rilegatura: Hardcover
• Edizione: 1992.
• Condizione: Fair

Descrizione articolo

Riassunto

The success of VHDL since it has been balloted in 1987 as an IEEE standard may look incomprehensible to the large population of hardware designers, who had never heared of Hardware Description Languages before (for at least 90% of them), as well as to the few hundreds of specialists who had been working on these languages for a long time (25 years for some of them). Until 1988, only a very small subset of designers, in a few large companies, were used to describe their designs using a proprietary HDL, or sometimes a HDL inherited from a University when some software environment happened to be developped around it, allowing usability by third parties. A number of benefits were definitely recognized to this practice, such as functional verification of a specification through simulation, first performance evaluation of a tentative design, and sometimes automatic microprogram generation or even automatic high level synthesis. As there was apparently no market for HDL's, the ECAD vendors did not care about them, start-up companies were seldom able to survive in this area, and large users of proprietary tools were spending more and more people and money just to maintain their internal system.

Contenuti

Preface. Introduction. Evolutionary Processes in Language, Software, and System Design; F.E. Marschner. Part I: Simulation. Timing Constraint Checks in VHDL -- a Comparative Study; F. Liu, A. Pawlak. Using Formalized Timing Diagrams in VHDL Simulation; M. Dufresne, K. Khordoc, E. Cerny. Switch-Level Models in Multi-Level VHDL Simulations; K. Khordoc, M. Biotteau, E. Cerny. Bi-Directional Switches in VHDL Using the 46 Value System; A. Stanculescu. Systems Real Time Analysis with VHDL Generated from Graphical SA-VHDL; M. Sipola, J.-P. Soininen, J. Kivelä. Delay Calculation and Back Annotation in VHDL Addressing the Requirements of ASIC Design; P. Connors, S. Nayak, J. Kraley, V. Berman. Part II: Synthesis. A VHDL-Driven Synthesis Environment; H. Konuk, F.E. Marschner. VHDL Specific Issues in High Level Synthesis; A. Postula. ASIC Design Using Silicon 1076; R.A. Cottrell. Generating VHDL for Simulation and Synthesis from a High-Level DSP Design Tool; L. Lundberg. Aspects of Optimization and Accuracy for VHDL Synthesis; J. Eliott, P. Harper. Part III: Formal Verifications and Semantics. Symbolic Computation of Hierarchical and Interconnected FSMS; A. Debreil, C. Berthet, A. Jerraya. Formal Semantics of VHDL Timing Constructs; A. Salem, D. Borrione. A Structural Information Model of VHDL; R.A.J. Marshall, H.J. Kahn. Formal Verification of VHDL Descriptions in Boyer-Moore: First Results; D. Borrione, L. Pierre, A. Salem. Developing a Formal Semantic Definition of VHDL; P.A. Wilsey. Part IV: Systems Level Design and Modelling. Approaching System Level Design; F.J. Rammig. Incremental Design -- Application of a Software-Based Method for High-LevelHardware Design with VHDL; A. Hohl. Introducing CASCADE Control Graph in VHDL; C. Le Faou, J. Mermet.