VLSI Design for Manufacturing: Yield Enhancement

One of the keys to success in the IC industry is getting a new product to market in a timely fashion and being able to produce that product with sufficient yield to be profitable. There are two ways to increase yield: by improving the control of the manufacturing process and by designing the process and the circuits in such a way as to minimize the effect of the inherent variations of the process on performance. The latter is typically referred to as "design for manufacture" or "statistical design". As device sizes continue to shrink, the effects of the inherent fluctuations in the IC fabrication process will have an even more obvious effect on circuit performance. And design for manufacture will increase in importance. We have been working in the area of statistically based computer aided design for more than 13 years. During the last decade we have been working with each other, and individually with our students, to develop methods and CAD tools that can be used to improve yield during the design and manufacturing phases of IC realization. This effort has resulted in a large number of publications that have appeared in a variety of journals and conference proceedings. Thus our motivation in writing this book is to put, in one place, a description of our approach to IC yield enhancement. While the work that is contained in this book has appeared in the open literature, we have attempted to use a consistent notation throughout this book.

1. Yield Estimation and Prediction.- 1.1. Introduction.- 1.2. The VLSI Fabrication Process.- 1.3. Disturbances in the IC Manufacturing Process.- 1.3.1. Process Disturbances.- 1.3.2. Process Related Deformations of IC Design.- 1.3.2.1. Geometrical Deformations.- 1.3.2.2. Electrical Deformations.- 1.3.3. General Characteristics of Process Disturbances.- 1.3.4. IC Performance Faults.- 1.4. Measures of Process Efficiency.- 1.4.1. Yield Estimation.- 1.4.2. Yield Prediction.- 1.4.3. Decomposition of the Design Yield Equations.- 1.5. Discussion.- 1.5.1. Relationships Between Manufacturing and Design Yields.- 1.5.2. Examples of Yield Analysis.- 1.5.3. Yield and Production Cost.- 1.6. Overview of the Sequel.- 2. Parametric Yield Maximization.- 2.1. Introduction.- 2.1.1. Definitions of Yield and Design Center.- 2.1.2. Design Centering By Simplicial Approximation.- 2.1.3. Design Centering Procedure.- 2.1.4. Scaling: Inscribing a Hyperellipsoid.- 2.1.5. Illustration of the Basic Method.- 2.2. Design Centering and Worst Case Design with Arbitrary Statistical Distributions.- 2.2.1. Norm Bodies and PDF Norms.- 2.2.2. Generalized Simplicial Approximation.- 2.2.3. Mixed Worst-Case Yield Maximization.- 2.2.4. Tolerance Assignment.- 2.3. Example of Worst Case Design.- 2.4. A Dimension Reduction Procedure.- 2.4.1. Design Centering in a Reduced Space.- 2.4.2. Discussion.- 2.5. Fabrication Based Statistical Design of Monolithic IC’s.- 2.5.1. Independently Designable Parameters in Yield Maximization of Monolithic IC’s.- 2.5.2. Process Simulation and Yield Maximization.- 3. Statistical Process Simulation.- 3.1. Introduction.- 3.2. Statistical Process Simulation.- 3.2.1. Methodology.- 3.2.2. Modeling of Process Disturbances.- 3.2.3. Process and Device Models for Statistical Simulation.- 3.2.4. Models of Ion Implantation.- 3.2.5. MOS Transistor Model.- 3.2.6. Structure of the Simulator.- 3.3. Tuning of Process Simulator with PROMETHEUS.- 3.3.1. Mathematical Formulation.- 3.3.2. Methodology of Solution.- 3.4. The Process Engineer’s Workbench.- 3.4.1. Process and Device Simulation.- 3.4.2. User Interaction-Process Synthesis.- 3.4.3. Internal Data Structures.- 3.4.4. User Interaction — Compiled Simulation.- 3.4.5. Extensions.- 4. Statistical Analysis.- 4.1. Statistical Timing Simulation.- 4.1.1. Overview.- 4.1.2. Our Approach.- 4.1.2.1. Timing reevaluation.- 4.1.3. Characterization.- 4.1.4. Delay decomposition.- 4.1.5. Nominal Simulation.- 4.1.6. Statistical Simulation.- 4.2. An Improved Worst-Case Analysis Procedure.- 4.2.1. Worst-Case Analysis Methodology.- 4.2.1.1. Algorithm for Worst-Case Analysis.- 4.2.2. A Software Package for Worst-Case Analysis.- 4.2.3. Examples.- 4.3. Optimal Device and Cell Design Using FABRICS.- 4.3.1. Proposed Methodology.- 4.3.2. Description of Experiment.- 4.3.3. Building the Regression Model.- 4.3.4. Performance Optimization.- 5. Functional Yield.- 5.1. Introduction.- 5.2. Basic Characteristics of Spot Defects.- 5.2.1. Defect Mechanisms.- 5.2.2. Defect Spatial Distribution.- 5.2.3. Distribution of Defect Radii.- 5.2.4. Distribution of Defect Radii Within Layer.- 5.3. Yield Modeling Using Virtual Layout.- 5.3.1. Critical Area.- 5.3.2. Spot Defect Related Yield Losses.- 5.3.3. Yield Losses Due to Lateral Process Deformations.- 5.3.4. Critical Area Computation Using Virtual Layout.- 5.3.5. Examples of Application of the Virtual Layout Method.- 5.4. Monte Carlo Approach to Functional Yield Prediction.- 5.4.1. The VLASIC Yield Simulator.- 5.4.2. Fault Analysis.- 5.4.3. VLASIC Implementation and Summarizing Discussion.- 5.5. Yield Computations for VLSI Cell.- 5.5.1. Probability of Failure (POF) for Simple Layout Patterns.- 5.5.2. POF for Macrocells.- 5.5.3. Implementation.- 6. Computer-Aided Manufacturing.- 6.1. Motivation.- 6.2. Overview of the CMU-CAM System.- 6.3. Statistical Process Control: The Unified Framework.- 6.3.1. Profit Function.- 6.4. CMU-CAM Software System.- 6.4.1. Decomposition.- 6.4.2. Modeling for Process Control.- 6.4.3. Statistical Quality Control.- 6.4.4. Acceptance and Rejection Criteria.- 6.4.5. Feed Forward Control.- 6.5. Computational Examples.- 6.5.1. Yield Enhancement.- 6.6. Conclusions.- References.